Data output circuit with reduced output noise

ABSTRACT

A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to output circuits, and more particularly,to improvement of a data output circuit used in a semiconductor memorydevice.

2. Description of the Background Art

FIG. 86 is a block diagram schematically showing an entire structure ofa general dynamic semiconductor memory device. Referring to FIG. 86, thedynamic semiconductor memory device includes a memory cell array 900 inwhich dynamic type memory cells MC are arranged in a matrix of rows andcolumns. In memory cell array 900, a word line WL is providedcorresponding to each row of memory cells. A pair of bit lines BL andZBL are provided corresponding to each column of memory cells MC. Amemory cell MC is provided corresponding to the crossing of one wordline WL and a pair of bit lines BL and ZBL. FIG. 86 representativelyshows one word line WL and a pair of bit lines BL and ZBL. Datacomplementary to each other appear on bit line BL and complementary bitline ZBL.

The dynamic semiconductor memory device further includes an addressbuffer 902 for generating internal row and column address signals RA andCA according to an externally applied address signal Ad, a row decoder904 for decoding an internal row address signal RA from address buffer902 to select a corresponding word line in memory cell array 900, and acolumn decoder 906 for decoding an internal column address signal CAfrom address buffer 902 to generate a column select signal for selectinga corresponding column (bit line pair) in memory cell array 900.

Address buffer 902 includes a row latch 905 activated in response to aninternal row address strobe signal ZRAS for latching an applied addresssignal Ad and generating an internal row address signal RA, and a columnlatch 907 responsive to an internal column address strobe signal ZCASfor latching an applied address signal Ad and generating an internalcolumn address signal CA.

A row address signal and a column address signal are provided to addressbuffer 902 in a time-division multiplexed manner. Internal row addressstrobe signal ZRAS is generated from RAS buffer 910 receiving anexternal row address strobe signal /RAS. Internal column address strobesignal ZCAS is generated from CAS buffer 912 activated in response toactivation of internal row address strobe signal ZRAS and receiving anexternal column address strobe signal /CAS.

The dynamic semiconductor memory device further includes a senseamplifier 914 for detecting and amplifying data of a memory cellconnected to a word line selected in memory cell array 900, and an IOgate 916 responsive to the column select signal from column decoder 906for connecting a corresponding column (a bit line pair) in memory cellarray 900 to an internal data bus 915. Sense amplifier 914 has itsoperation controlled by a clock control circuit 918 responsive tointernal row address strobe signal ZRAS for generating a sense amplifieractivation signal (not shown explicitly) at a predetermined timing.Clock control circuit 918 also controls the activation/inactivation ofrow decoder 904.

The semiconductor memory device further includes an ATD circuit 920 fordetecting a change in internal column address signal CA from columnlatch 907 for generating an address transition detection signal φATDwhen the change is detected, an input/output control circuit 922 forgenerating a timing control signal determining data input/output timingaccording to internal column address strobe signal ZCAS from CAS buffer912, an external write/read designating signal (write enable signal)/WE,and address transition detection signal φATD, an input circuit 924responsive to a data write designating signal (not explicitly shown)from input/output control circuit 922 for transmitting internal writedata according to external data D to internal data bus 915, and anoutput circuit 926 responsive to a data output permission signal frominput/output control circuit 922 for generating and providing externalreadout data Q from the internal readout data appearing on internal databus 915.

Write enable signal /WE specifies a data writing operation whenattaining an L level (logical low), and a data readout operation whenattaining an H level (logical high). The operation will now be describedbriefly.

When external row address strobe signal /RAS is pulled down to an Llevel, which in turn causes internal row address strobe signal ZRAS fromRAS buffer 910 to attain an L level, a memory cycle is initiated. Inresponse to internal row address strobe signal ZRAS attaining an Llevel, row latch 904 in address buffer 902 latches a currently appliedaddress signal Ad to generate and provide to row decoder 904 an internaladdress signal RA. Clock control circuit 918 provides an activationsignal to row decoder 904 according to this internal row address strobesignal ZRAS at L level. Row decoder 904 decodes internal row addresssignal RA to select a corresponding word line in memory cell array 900.As a result, data in a memory cell connected to the selected word lineis read out on a corresponding bit line BL (or ZBL). Then, senseamplifier 914 is activated according to a sense amplifier activationsignal (not explicitly shown) from clock control circuit 918, wherebythe potentials on bit lines BL and ZBL are amplified differentially.

Following the fall of external row address strobe signal /RAS, externalcolumn address strobe signal /CAS attains an L level, and internalcolumn address strobe signal ZCAS of an L level is generated from CASbuffer 912 attaining an enable state by internal row address strobesignal ZRAS of an L level. In response to internal column address strobesignal ZCAS, column latch 907 latches an applied address signal Ad togenerate an internal column address signal CA. Column decoder 906decodes this internal column address signal CA to generate a signal forselecting a column (a bit line pair) in memory cell array 900. Followingthe sensing and amplification of memory cell data on each bit line pairby sense amplifier 914, IO gate 916 responds to a column select signalfrom column decoder 906 to conduct, whereby a corresponding bit linepair is connected to internal data bus 915. Then, data writing orreading is carried out via input circuit 924 or output circuit 926.

FIG. 87 shows a structure of a 1-bit data output unit of output circuit926. When the semiconductor memory device of FIG. 86 has a structurewhere multibit data such as 4 bits and 8 bits are input/output, aplurality of the input/output units of FIG. 87 are provided according tothe number of bits of data.

Referring to FIG. 87, output circuit 926 includes an inverter 5 forinverting data ZDD appearing on an internal data bus line 915 b, a2-input AND gate 3 receiving an output permission signal OEM and anoutput of inverter 5, a 2-input AND circuit 4 receiving outputpermission signal OEM and internal readout data ZDD, a first outputdrive transistor 1 responsive to an output of AND circuit 3 for drivingan output node 6 to a level of a power supply potential Vcc, and asecond drive transistor 2 responsive to an output of AND circuit 4 fordischarging output node 6 to the level of a ground potential GND. Drivetransistors 1 and 2 are both formed of an n channel MOS (insulated gatetype) transistor. Output permission signal OEM is generated according tointernal column address strobe signal ZCAS from input/output controlcircuit 922 shown in FIG. 86 and address transition detection signalφATD. The operation of the output circuit shown in FIG. 87 will now bedescribed with reference to the operation waveform diagram of FIG. 88.

At an elapse of a predetermined time period from the attaining ofinternal column address strobe signal ZCAS to L level, a signal of alogic opposite to that of data in the selected memory cell istransmitted on internal data bus line 915 b. Internal data bus line 915b is precharged to the level of an intermediate potential during thestandby state. FIG. 88 shows the state where a data signal of an L levelappears on internal data bus line 915 b.

During the period when output permission signal OEM attains an L level,both outputs of AND circuits 3 and 4 attain an L level, and drivetransistors 1 and 2 are both OFF. Thus, the high impedance state (Hi-Z)of output node 6 is maintained.

When output permission signal OEM attains an H level, AND circuits 3 and4 are enabled. Data signal ZDD on internal data bus line 915 b attainsan H level and the output of inverter 5 attains an L level. Therefore,according to output permission signal OEM of an H level, the output ofAND circuit 4, i.e., the potential of node N2 is pulled up to an Hlevel, and second drive transistor 2 is turned on. Output node 6 isdischarged to the level of ground potential GND via second drivetransistor 2, whereby output data Q of an L level is provided.

When data signal ZDD attains an L level, the output of AND circuit 3,i.e., the potential of node N1 is pulled up to an H level in response tothe rise of output permission signal OEM, whereby first drive transistor1 is turned on. This causes output node 6 to be charged to a potentiallevel lower than power supply potential Vcc by the threshold voltage oftransistor 1. As a result, output data Q attains an H level. In general,a booster is provided to compensate for the threshold voltage loss ofthe output data.

Drive transistors 1 and 2 have their current driving capability set todrive a great current flow such as several mA in order tocharge/discharge an external load at high speed to provide dataspeedily. A semiconductor memory device is sealed in a package. In thiscase, output node 6 is connected to a frame lead forming an outputterminal via a bonding wire, as shown in FIG. 89. In FIG. 89, thisbonding wire and frame lead are shown as output terminal 930. Not onlyparasitic capacitance C, but also parasitic inductance L are present insuch a bonding wire and frame lead. A current change in parasiticinductance L generates a voltage represented by the equation of:V=−L·di/dtwhere di/dt is the time differential of a current i flowing throughinductance L.

When drive transistors 1 and 2 are both turned off, output node 6attains an high impedance state where the potential level of theprevious output data Q is maintained. Therefore, when data Q of an Llevel is to be output after output data Q of an H level is provided,ringing occurs in output node 6 since output node 6 is discharged viadrive transistor 2 having a great current driving capability, as shownin FIG. 90A.

When data Q of an H level is to be output after output data Q of an Llevel is provided, output node 6 is charged via drive transistor 1having a great current driving capability. Therefore, overshootingoccurs as shown in FIG. 90B since there is a great change in current inparasitic inductance L.

Also in the structure of maintaining output node 6 at an intermediatepotential differing from the structure of maintaining output node 6 at ahigh impedance state, the output node precharged to the intermediatepotential is charged/discharged according to the logic of the data to beoutput via drive transistor 1 having a great current driving capability.Therefore, the similar occurrence of ringing at the output node isencountered.

When ringing such as the above-described overshooting or undershootingoccurs, there is a problem that data cannot be read out until the outputdata is stabilized, so that e the access time is increased. When theamplitude of generated undershooting is great, a great voltage isapplied across the gate and drain (node terminal connected to outputnode 6) of output drive transistor 1, resulting in the problem that thebreakdown voltage characteristic of transistor 1 is degraded. The sameproblem is encountered in drive transistor 2.

An approach of carrying out the drive of an output node in two stages isconsidered to prevent the above-described problem of ringing, as shownin FIG. 91. FIG. 91 shows the structure of only the portion associatedwith discharging the output node in two stages.

Referring to FIG. 91, the output circuit includes drive transistors 2 aand 2 b connected in parallel between output node 6 and a groundpotential node. Drive transistors 2 a and 2 b are formed of n channelMOS transistors. The current driving capability of drive transistor 2 ais set smaller than that of drive transistor 2 b. This is realized byadjusting the channel length or the channel width of the transistor. Theoutput of AND circuit 4 receiving output permission signal OEM andinternal readout data signal ZDD is provided to the gate of drivetransistor 2 a. A delay stage 7 for delaying the signal potential onnode N2 for a predetermined time and an AND circuit 8 for receiving anoutput of delay stage 7 and the signal potential on node N2 are providedto control the on/off of drive transistor 2 b. The output of AND circuit8 is provided to the gate of drive transistor 2 b. Delay stage 7includes an even number of inverters (four inverters in FIG. 91) todelay an applied signal for a predetermined time. The operation of theoutput circuit of FIG. 91 will now be described with reference to theoperation waveform diagram of FIG. 92.

When internal column address strobe signal ZCAS attains an L level of anactive state, a column select operation is initiated, and data of aselected memory cell is transmitted on internal data bus line 915 b.When output permission signal OEM is pulled up to an H level, thepotential of node N2 attains an H level, whereby drive transistor 2 a isturned on. As a result, output node 6 is discharged mildly. The outputof delay stage 7 still attains a low level, and the potential of node N3is at an L level. Drive transistor 2 b is still turned off.

When the output of the delay stage 7 attains an H level at an elapse ofa predetermined time period, the output of AND circuit 8 is pulled up toan H level, whereby drive transistor 2 b is turned on. As a result,output node 6 is discharged at a high speed. The potential of outputnode 6 is sufficiently lowered when drive transistor 2 b is turned on.Therefore, there is almost no ringing even when output node 6 isdischarged at high speed. This is because the maximum amplitude in a RLCcircuit at the occurrence of damping oscillation is proportional to thevoltage value where that rapid discharging is carried out.

A static column mode is a well known operation mode in a dynamicsemiconductor memory device. As shown by the operation waveform diagramof FIG. 93, data is input/output in random by entering only an addresssignal with respect to one row of memory cells specified by a rowaddress signal X in the static column mode.

More specifically, row address strobe signal ZRAS is first pulled downto an L level, whereby a row address signal is entered to select a wordline. The data of memory cells connected to the selected word line aresensed and amplified by the sense amplifiers to be latched. Data of acorresponding column address is output by entering a column addresssignal Y asynchronously and maintaining the same for a predeterminedtime. In this static column mode, column address strobe signal ZCAS hasthe function of output enable, not the function of designating a columnaddress latch, and is maintained at L level. In this static column mode,data can be output at high speed without toggling of column addressstrobe signal /CAS to enter a column address signal.

It is to be noted that output permission signal OEM is maintained at anH level as shown in FIG. 93 in a static column mode. Therefore, one ofdrive transistors 1 and 2 a is turned on, and output node 6 ismaintained at an H or L level. When data of an L level is to be providedfollowing a data output of an H level, the potential amplitude of outputnode 6 is increased to generate ringing if the delay time of delay stage7 is too short in such a static column mode operation. If the delay timeof delay stage 7 is increased to prevent such generation of ringing, theaccess time will be lengthened to degrade the advantage of high speedaccess of the static column mode.

A delay stage is formed of an inverter. In general, a CMOS inverter oflow power consumption is used as such an inverter. An MOS transistor hasits driving capability determined depending upon the gate voltage. Morespecifically, the operating speed of the inverter is increased as theoperating power supply voltage of the inverter forming the delay stagebecomes higher, to result in a shorter delay time of the delay stage.Furthermore, an increase in the operating temperature causes reductionin the operating speed of the MOS transistor (due to increase in thethreshold voltage and the channel resistance by generation of hotcarriers). Therefore, as the operating temperature increases, theoperating speed of the inverter forming the delay stage is reduced toincrease the delay time of the delay stage. Such a variation in thedelay time of the delay stage makes different the on-timing of drivetransistor 2 b shown in FIG. 91. In this case, a shorter delay time maycause drive transistor 2 b to be turned on when the potential of theoutput node is not lowered sufficiently. Therefore, output node 6 willbe discharged at high speed to result in generation of ringing. Thedriving capability of the output drive transistor is increased when thepower supply voltage is increased or at a low operating temperature.Therefore, there is a problem that ringing occurs more easily.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an output circuit thatcan output a signal stably at high speed without generation of ringing.

Another object of the present invention is to provide an output circuitin a semiconductor memory device that can output a data signal stablywithout increase in the access time.

An output circuit according to an aspect of the present inventionincludes an adjustment unit coupled to a data output node for adjustingthe charging/discharging speed of the data output node when a dataoutput permission signal is activated, or for driving the data outputnode to the level of a predetermined potential when the data outputpermission signal is inactivated so as to reduce ringing at the dataoutput node at the time of data output. The adjustment unit can berealized in various manners.

An output circuit according to another aspect of the present inventionincludes a first drive element coupled between an output node and areference voltage node and responsive to an internal signal for drivingthe output node and an output pad to the level of the voltage on thereference voltage node with a first current driving capability, a seconddrive element connected between the output node and the referencevoltage node, having a current driving capability greater than that ofthe first drive element, and rendered conductive at a timing behind thatof the first drive element for driving the output node and the outputpad to the voltage level on the reference voltage node, and a noiseabsorbing unit provided between the first drive element and the outputpad for absorbing a noise voltage appearing on the output pad.

According to the one aspect, the charging/discharging speed or thepotential of the data output node is adjusted by the adjustment unit toreduce the |di/dt| of the data output node to suppress generating ofringing. In the output circuit of the another aspect, a protectioncircuit for absorbing excessive noise such as a surge voltage isprovided between the output pad and the drive transistor of a smallcurrent driving capability.

Therefore, the drive transistor with a small current driving capabilityand a low breakdown voltage can be prevented from being damaged byexcessive noise such as a surge voltage. Therefore, an output circuitwith high immunity to noise can be provided.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a structure of an output control circuit according to afirst embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing an operation of the outputcontrol circuit of FIG. 1.

FIG. 3 shows a first modification of the first embodiment of the presentinvention.

FIG. 4 is a diagram used for explaining the operation of the outputcontrol circuit of FIG. 3.

FIG. 5 shows a structure of an output permission signal generationcircuit of FIG. 1.

FIG. 6 is a signal waveform diagram representing an operation of theoutput permission signal generation circuit of FIG. 5.

FIGS. 7 and 8 show second and third modifications, respectively, of thefirst embodiment of the present invention.

FIG. 9 shows a structure of an output control circuit according to asecond embodiment of the present invention.

FIGS. 10 and 11 are signal waveform diagrams representing the operationof the output control circuit of FIG. 9.

FIG. 12 shows a modification of the second embodiment of the presentinvention.

FIG. 13 is a signal waveform diagram representing an operation of theoutput control circuit of FIG. 12.

FIG. 14 is a diagram for showing the timing relationship of an outputdesignating signal and an output permission signal, and the relationshipof resulting output signals and these signals.

FIG. 15 is a diagram used for explaining the timing relationship of anoutput designating signal and an output permission signal, and therelationship of output data signals and these signals.

FIG. 16 shows a structure of an output control circuit according to athird embodiment of the present invention.

FIGS. 17A and 17B are signal waveform diagrams representing an operationof the output control circuit of FIG. 16.

FIGS. 18A and 18B show a structure and a signal waveforms, respectively,of a first modification of the third embodiment of the presentinvention.

FIGS. 19 and 20 show a structure of a second modification and a thirdmodification, respectively, of the third embodiment of the presentinvention.

FIG. 21 shows a modification of the NAND circuit shown in FIG. 20.

FIG. 22 is a signal waveform diagram representing an operation of thecircuit of FIG. 21.

FIG. 23 shows a structure of an output control circuit according to afourth embodiment of the present invention.

FIGS. 24A and 24B are signal waveform diagrams representing an operationof the output control circuit of FIG. 23.

FIG. 25 is a first modification of the output control circuit of thefourth embodiment of the present invention.

FIGS. 26A and 26B are signal waveform diagrams representing an operationof the output control circuit of FIG. 25.

FIG. 27 shows a second modification of the output control circuit of thefourth embodiment of the present invention.

FIGS. 28A and 28B are signal waveform diagrams representing an operationof the output control circuit of FIG. 27.

FIG. 29 shows a third modification of the output control circuitaccording to a fourth embodiment of the present invention.

FIGS. 30A and 30B are signal waveform diagrams showing an operation ofthe output control circuit of FIG. 29.

FIG. 31 shows a fourth modification of the output control circuit of thefourth embodiment of the present invention.

FIGS. 32A and 32B are signal waveform diagrams representing theoperation of the output control circuit of FIG. 31.

FIGS. 33 and 34 show a fifth modification and a sixth modification,respectively, of the output control circuit of the fourth embodiment ofthe present invention.

FIGS. 35A and 35B are signal waveform diagrams representing an operationof the output control circuit of FIG. 34.

FIG. 36 shows a seventh modification of the output control circuit ofthe fourth embodiment of the present invention.

FIGS. 37, 38, and 39 are signal waveform diagrams representing anoperation of the output control circuit of FIG. 36.

FIG. 40 shows an eighth modification of the output control circuit ofthe fourth embodiment of the present invention.

FIGS. 41 and 42 are signal waveform diagrams representing an operationof the output control circuit of FIG. 40.

FIGS. 43 and 44 show a ninth modification and a tenth modification,respectively, of an output control circuit according to the fourthembodiment of the present invention.

FIGS. 45A and 45B show the temperature and voltage dependentcharacteristics, respectively, of a first control voltage used in afifth embodiment of the present invention.

FIGS. 46A and 46B are diagrams representing the temperature and voltagedependent characteristics, respectively, of a second control voltageused in the fifth embodiment.

FIGS. 47A and 47B are diagrams showing the structure and the operationcharacteristics, respectively, of the components of a delay circuit usedin the fifth embodiment of the present invention.

FIGS. 48A and 48B are diagrams showing the structure and the operationcharacteristics, respectively, of the components of a delay circuit usedin the fifth embodiment of the present invention.

FIGS. 49A and 49B are diagrams showing the structure and the operationcharacteristics, respectively, of the components of a delay circuit usedin the fifth embodiment of the present invention.

FIGS. 50A and 50B show a first application and an operation waveformsthereof, respectively, of the fifth embodiment of the present invention.

FIGS. 51A and 51B show a second application and an operation waveformsthereof, respectively, of the fifth embodiment of the present invention.

FIGS. 52A and 52B show a third application and an operation waveformsthereof, respectively, of the fifth embodiment of the present invention.

FIGS. 53A and 53B show a fourth application and an operation waveformsthereof, respectively, of the fifth embodiment of the present invention.

FIG. 54 schematically shows a circuit configuration for generating firstand second control voltages.

FIGS. 55A and 55B show the voltage/temperature dependent characteristicsof a first reference voltage and a specific structure, respectively, ofa VREF1 generation circuit shown in FIG. 54.

FIGS. 56A, 56B, and 56C show the voltage dependent characteristics,temperature dependent characteristics of the second reference voltage,and a specific structure, respectively of a VREF2 generation circuit ofFIG. 54.

FIGS. 57A and 57B show input/output voltage of first and seconddifferential amplify circuits, respectively, of FIG. 54.

FIG. 58 shows the voltage/temperature dependent characteristics of anoperating power supply voltage used in a modification of the fifthembodiment of the present invention.

FIGS. 59A and 59B show a modification and an operating characteristicsthereof, respectively, of the fifth embodiment of the present invention.

FIG. 60 schematically shows a structure of an output circuit accordingto a sixth embodiment of the present invention.

FIG. 61 schematically shows a structure of the output circuit of FIG.60.

FIG. 62 shows a structure of a voltage adjuster shown in FIG. 60.

FIG. 63 is a signal waveform diagram representing an operation of thevoltage adjuster of FIG. 62.

FIG. 64 shows a first modification of the sixth embodiment of thepresent invention.

FIG. 65 schematically shows a structure of an output circuit accordingto the first modification of the sixth embodiment of the presentinvention.

FIG. 66 shows a structure of a voltage adjuster according to an outputcircuit of a seventh embodiment of the present invention.

FIGS. 67A and 67B show a structure of an adjusting voltage Vccpgeneration circuit and a Vbsg generation circuit, respectively, of FIG.66.

FIG. 68 shows a structure of an output circuit according to an eighthembodiment of the present invention.

FIGS. 69 and 70 are signal waveform diagrams representing an operationof the output circuit of FIG. 68.

FIG. 71 shows a structure of an output circuit according to a ninthembodiment of the present invention.

FIG. 72 shows a modification of the ninth embodiment of the presentinvention.

FIGS. 73A and 73B show a structure and operation, respectively, of anoutput circuit according to a tenth embodiment of the present invention.

FIGS. 74A and 74B show a structure and an operation, respectively, of amodification of the tenth embodiment of the present invention.

FIGS. 75A and 75B show a structure and operation, respectively, of anoutput circuit according to an eleventh embodiment of the presentinvention.

FIG. 76 shows a structure of an output circuit according to a twelfthembodiment of the present invention.

FIGS. 77A and 77B show an external power supply voltage and temperaturedependent characteristics, respectively, of a reference voltage VREF3provided from a reference voltage generation circuit of FIG. 76.

FIGS. 78A and 78B show temperature and external power supply voltagedependent characteristics, respectively, of a power supply voltage VccQappearing on a reference power supply node of FIG. 76.

FIG. 79 shows an application of the twelfth embodiment of the presentinvention.

FIGS. 80A and 80B represent a structure and operation, respectively, ofan output circuit according to a thirteenth embodiment of the presentinvention.

FIG. 81 shows a structure of a semiconductor device of the thirteenthembodiment of the present invention.

FIGS. 82A and 82B are waveform diagrams representing a signal outputoperation of the semiconductor device of FIG. 81.

FIG. 83 shows a modification of the thirteenth embodiment of the presentinvention.

FIGS. 84 and 85 show a structure of an output circuit according to afourteenth embodiment and a fifteenth embodiment, respectively, of thepresent invention.

FIG. 86 schematically shows an entire structure of a conventionaldynamic semiconductor memory device.

FIG. 87 shows a structure of a conventional output circuit.

FIG. 88 is a signal waveform diagram representing an operation of theoutput circuit shown in FIG. 87.

FIG. 89 shows a parasitic capacitance and a parasitic inductance at anoutput node.

FIGS. 90A and 90B are diagrams for explaining ringing generated by theparasitic inductance shown in FIG. 89.

FIG. 91 shows a possible modification of an output control circuit.

FIG. 92 is a signal waveform diagram showing an operation of the outputcontrol circuit of FIG. 91.

FIG. 93 shows the relationship between an output permission signal and acolumn address strobe signal of FIG. 91.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1

FIG. 1 shows a structure of an output circuit according to a firstembodiment of the present invention.

The portion for driving output node 6 to the level of ground potentialis shown in FIG. 1. Overshooting at the output node can be prevented byapplying a structure similar to that shown in FIG. 1 to the portiondriving output node 6 to the level of power supply potential Vcc.

Referring to FIG. 1, the output circuit 926 includes a 2-input ANDcircuit 10 for receiving an output permission signal OEM and a readoutdata signal DD on an internal data bus line 915 a, an AND circuit 11 forreceiving output permission signal OEM and a complementary internalreadout data signal ZDD on an internal data bus line 915 b, a firstdrive transistor 1 responsive to an output of AND circuit 10 for drivingoutput node 6 to the level of power supply potential Vcc, a drivetransistor 2 a responsive to an output of AND circuit 11 for drivingoutput node 6 to the level of a ground potential, and a drive transistor2 b provided in parallel to drive transistor 2 a. The current drivingcapability of drive transistor 2 a is set smaller than that of drivetransistor 2 b. Drive transistors 1, 2 a, 2 b are formed of n channelMOS transistors. The difference in the current driving capability ofdrive transistors 2 a and 2 b are implemented by appropriately selectingthe size or gate (channel) width, or the ratio of the gate width to thegate length thereof.

Output circuit 926 further includes an invert delay circuit 15 fordelaying and inverting the logic of an output of AND circuit 10 i.e., asignal potential of node N1, a 2-input NOR circuit 16 for receiving asignal on node N1 and an output of delay circuit 15, an invert delaycircuit 17 for delaying output permission signal OEM for a predeterminedtime and inverting the logic thereof, a 2-input NOR circuit 18 forreceiving an output of invert delay circuit 17 and output permissionsignal OEM, an invert delay circuit 19 for delaying a data outputdesignating signal DOT generated at a change of a column address signalfor a predetermined time and inverting the logic thereof, a NOR circuit20 for receiving output designating signal DOT and an output of invertdelay circuit 19, a 2-input OR circuit 21 for receiving outputs of NORcircuits 18 and 20, and a 2-input NAND circuit 22 for receiving outputsof NOR circuit 16 and an OR circuit 21.

2-input NOR circuit 16 generates a one shot pulse signal of a positivepolarity having a time width determined by the delay time of invertdelay circuit 15 when the potential of node N1 is pulled down to an Llevel from an H level.

2-input NOR circuit 18 generates a one shot pulse signal of a positivepolarity having a time width determined by the delay time of invertdelay circuit 17 when output permission signal OEM is pulled down to anL level from an H level.

2-input NOR circuit 20 generates a one shot pulse signal of a positivepolarity having a time width determined by a delay time of delay circuit19 when output designating signal DOT is pulled down to an L level froman H level. Output designating signal DOT is generated in a form of aone shot pulse that attains an L level for a predetermined time when thecolumn address signal changes.

Output circuit 926 further includes a delay circuit 12 for delaying anoutput of AND circuit 11, i.e. a signal on node N2 for a predeterminedtime period, a 2-input NAND circuit 13 for receiving a signal on node N2and an output of delay circuit 12, and a 2-input NAND circuit 14 forreceiving outputs of NAND circuits 13 and 22. Drive transistor 2 b isturned on when NAND circuit 14 provides an output of an H level. Theoperation of the output circuit shown in FIG. 1 will now be describedwith reference to the operational waveform diagram of FIG. 2.

A data readout operation in which a selected memory cell stores data “L”will be described. When internal column address strobe signal ZCAS ispulled down to an L level, an internal column address signal Y1 isgenerated. This generation of internal column address signal Y1 from anaddress buffer causes an address transition detection circuit togenerate an address transition detection signal φATD in a one shot pulseform. Output designating signal DOT attains an L level for apredetermined time according to this address transition detectionsignal. Internal data bus lines 915 a and 915 b are precharged to an Llevel according to output designation signal DOT. In a standby state,output permission signal OEM and the potential of nodes N1 and N2 attainan L level, and all drive transistors 1, 2 a, 2 b are turned off.

A pulse having a time width of the delay time of invert delay circuit 19is generated from NOR circuit 20 according to one shot outputdesignating signal DOT, whereby OR circuit 21 provides an output of an Hlevel. The potential of nodes N1 and N4 are still at the L level and Hlevel, respectively. Output permission signal OEM attains an L level,and the potential of node N5 attains an H level. Therefore, NAND circuit22 (potential of node N8) does not change its H level output even whenoutput designating signal DOT attains an L level for a predeterminedtime.

Also, the potential of node N2 attains an L level, the output of NANDcircuit 13 attains an H level, and the output of NAND circuit 14(potential of node N9) attains an L level.

In response to output permission signal OEM attaining an active state ofan H level, the potential of node N1 is driven to an L level, and thepotential of node N2 is driven to an H level. Thus, transistor 1maintains its off state. In contrast, drive transistor 2 a is turned on,and the potential of output node 6 is gently discharged to the level ofa ground potential. At an elapse of the delay time of delay circuit 12,the output of delay circuit 12 attains an H level, and the output of theNAND circuit 13 attains an L level. As a result, the output of NANDcircuit 14 attains an H level to turn on drive transistor 2 b.Therefore, drive transistor 2 b discharge output node 6 to the level ofground potential at high speed.

In response to a change of external column address signal Ad, outputdesignating signal DOT attains an L level for a predetermined time. Thisoperation mode is called a static column mode. When output designatingsignal DOT attains an L level, it indicates that the data Q appearing onoutput node 6 is invalid to prepare for the next cycle. Morespecifically, it can be said that output designating signal DOTindicates that the current data appearing on output node 6 should bemade invalid. In response to the transition of output designating signalDOT to an L level, internal data lines 915 a and 915 b are bothprecharged to the level of a ground potential again.

As a result, the potential of both nodes N1 and N2 are pulled down to anL level, and transistors 1, 2 a and 2 b are turned off. At an elapse ofa predetermined time period (the time required for data of a bit linepair selected according to a column address signal to be read out to aninternal data bus) from the fall of output designating signal DOT to anL level, the potential of internal data bus lines 915 a and 915 b attainan H level and an L level, respectively, according to the read out data.As a result, drive transistor 1 is turned on, and output node 6 ischarged to the level of power supply potential Vcc.

When internal column address strobe signal ZCAS attains an inactivestate of an H level, output permission signal OEM is also driven to an Llevel. In response, a one shot pulse is generated from NOR circuit 18,and the potential of node N1 is driven to an L level from an H level,and drive transistor 1 is turned off. In response to the fall of thepotential of node N1, a one shot pulse signal is generated on node N4from NOR circuit 16. Invert delay circuit 15 is formed of five stages,for example, of inverters. Invert delay circuit 17 is formed of threestages, for example, of inverter circuits. The delay time of invertdelay circuit 15 is set longer than that of invert delay circuit 17.Therefore, when the potential of node N4 attains an H level, thepotential of node N7 (output of OR circuit 21) is driven to an H level,whereby a one shot pulse signal of an L level having a time widthdetermined by the delay time of invert delay circuit 17 is generatedfrom NAND circuit 22 onto node N8. In response, a one shot pulse signalof an H level is generated from NAND circuit 14 on node N9, and drivetransistor 2 b is turned on. As a result, output node 6 is dischargedfrom the level of power supply potential Vcc to the ground potential fora predetermined time, and the potential of output node 6 attains anintermediate potential level between power supply potential Vcc andground potential GND. The intermediate potential level of output node 6is determined by the driving capability of drive transistor 2 b,external load, and the delay time of invert delay circuit 17.

As described above, the potential of output node 6 attains the level ofan intermediate potential even when a structure for maintaining outputnode 6 at an intermediate potential level is not provided since drivetransistor 2 b discharging output node 6 to the level of groundpotential is turned on for a predetermined time after data of an H levelis read out. This means that output node 6 is driven from the level ofan intermediate potential regardless of whether the data read out at thenext cycle attains an H level or an L level. Therefore, the outputamplitude is small and no ringing is generated. Thus, a stable outputsignal Q can be obtained at high speed. Even in the case where data “L”is output after an outputting of data “H” in a static column mode,ringing does not occur in output node 6, so that a stable output signalQ can be provided.

By providing the structure shown in FIG. 1 to drive transistor 1, outputnode 6 can be pulled up after reading out of data “L”, to be set to thelevel of an intermediate potential, as shown in the broken line in FIG.2.

FIG. 3 shows a structure of an output circuit where a control system isprovided for reading out data of both “H” and “L”. Referring to FIGS. 1and 3, each of control blocks 40 a and 40 b includes NOR circuits 16,18, 20, OR circuit 21, NAND circuit 22, and invert delay circuits 15,17, 19 shown in FIG. 1. Delay circuits 12 a and 12 b correspond to delaycircuit 12, NAND circuits 13 a and 13 b correspond to NAND circuit 13,and NAND circuits 14 a and 14 b correspond to NAND circuit 14.

By employing the circuit configuration shown in FIG. 3, the output nodeis driven to an intermediate potential according to output designatingsignal DOT in a static column mode operation, and output node 6 isdriven to an intermediate potential according to output permissionsignal OEM at the completion of a memory cycle, as shown in FIG. 4.Therefore, a stable output signal can be generated with no ringing sinceoutput node 6 is driven to an H or n L level from the intermediatepotential level in either case.

FIG. 5 shows a structure of a generation system of an output designatingsignal and an output permission signal. The control signal generationsystem of FIG. 5 is included in the input/output control circuit shownin FIG. 86.

Referring to FIG. 5, an output control signal generation circuitincludes a one shot pulse generation circuit 50 activated in response toan internal row address strobe signal ZRAS for generating a one shotpulse signal of an L level in response to address transition detectionsignal φATD, a delay circuit 51 for delaying internal column addressstrobe signal ZCAS for a predetermined time period, a one shot pulsegeneration circuit 52 responsive to the rise of output designatingsignal DOT from one shot pulse generation circuit 50 for generating aone shot pulse signal, a gate circuit 57 receiving an internal writeenable signal ZWE and internal column address strobe signal ZCAS forproviding a signal of an H level when a data readout operation isdesignated, a 2-input NAND circuit 55 for receiving outputs of one shotpulse generation circuit 52 and gate circuit 57, an inverter circuit 54for inverting a delayed column address strobe signal ZCASE from delaycircuit 51, a flipflop 56 set in response to a signal of an L level frominverter circuit 54, and reset in response to a signal of an L levelfrom NAND circuit 55, and an inverter circuit 58 for inverting theoutput of flipflop 56. Output permission signal OEM is generated frominverter circuit 58.

One shot pulse generation circuit 52 includes a delay circuit 61 fordelaying output designating signal DOT for a predetermined time period,and a 2-input AND circuit 62 for receiving an output of delay circuit 61and output designating signal DOT. Delay circuit 61 is formed of an evennumber of inverters (two inverter circuits in the structure shown inFIG. 5).

Flipflop 56 includes two cross-coupled NAND circuits NA1 and NA2. NANDcircuit NA1 has one input receiving an output of inverter circuit 54,and the other input receiving an output of NAND circuit NA2. NANDcircuit NA2 has one input receiving an output of NAND circuit 55, andthe other input receiving an output of NAND circuit NA1. The output ofNAND circuit NA1 is applied to inverter circuit 58.

Gate circuit 57 provides a signal of an H level when internal columnaddress strobe signal ZCAS attains L level and write enable signal ZWEattains an H level. When the employed dynamic semiconductor memorydevice has a structure in which an output enable signal ZOE is used,gate circuit 57 may be replaced with an inverter that inverts thisoutput enable signal ZOE. Any structure may be used as long as a signalof an H level is output at node N10 in a data readout operation.

The control signal generation circuit further includes an invertercircuit 59 for inverting output designating signal DOT from one shotpulse generation circuit 50, and precharge transistors 60 a and 60 bresponsive to an output of inverter circuit 59 for precharging internaldata bus lines 915 a and 915 b to the level of ground potential.Precharge transistors 60 a and 60 b are both formed of an n channel MOStransistor. The operation of the control signal generation system ofFIG. 5 will now be described with reference to the operation waveformdiagram of FIG. 6.

When row address strobe signal ZRAS attains an inactive state of an Hlevel, output designating signal DOT attains an L level, and columnaddress strobe signal ZCAS attains an inactive state of an H level.Thus, the potentials of nodes N11, N12 and N13 attain an L level, andthe potentials of nodes N10, N14 and N15 attain an H level.

A memory cycle is initiated when row address strobe signal ZRAS attainsan active state of an L level. In response to internal row addressstrobe signal ZRAS attaining an L level, one shot pulse generationcircuit 50 is activated to pull up output designating signal DOT whichis an output thereof to an H level. At an elapse of a predetermined timefrom transition of output designating signal DOT to H level, a signal ofan H level is provided from one shot pulse generation circuit 52. Whenthe column address signal changes, an address transition detectionsignal φATD is responsively generated. It is to be noted that in asemiconductor memory device where a static column mode of operation ispossible, the column address strobe signal has only the function of anoutput enable signal, and not the function of instructing an addresslatch. In response to address transition detection signal φATD, outputdesignating signal DOT attains an L level for a predetermined time. Thefall of output designating signal DOT to an L level causes the output ofone shot pulse generation circuit 52 (output at node N12) to attain an Llevel. A signal of an L level having a pulse width longer than outputdesignating signal DOT by the delay time of delay circuit 61 is outputfrom one shot pulse generation circuit 52.

When a signal of an L level is provided on node 12 from one shot pulsegeneration circuit 52, NAND circuit 55 provides a signal of an H levelon node N13.

Then, when column address strobe signal ZCAS attains an L level, delayedcolumn address strobe signal ZCASE which attains an L level at an elapseof a predetermined time is generated from delay circuit 51. A signal ofan H level is provided from inverter circuit 54 on node N11 by thisdelayed column address strobe signal ZCASE attaining an L level.

The potential of node N14 attains an H level, and node N15 attains an Llevel in response to the rise of the potential of node N13. When thepotential of node 15 attains an L level in response to the rise of thepotential of node N13, the potential of node N15 is pulled up to an Hlevel, whereby a signal of an L level is provided from NAND circuit N1to node N14. In response to the fall of the potential of node N14, anoutput signal of inverter circuit 58, i.e. output permission signal OEMattains an H level.

The potential of node N14 is fixed at the L level output permissionsignal OEM attains an H level during the period in which internal columnaddress strobe signal ZCAS (ZCASE) is at an L level and the potential ofnode N15 is at an H level.

Even when output designating signal DOT is driven to an L level and thepotential of node N13 is driven to an H level when delayed internalcolumn strobe signal ZCASE attains an L level, the potential of node N14is at an L level, and the potential of node N15 does not change.

More specifically, output permission signal OEM maintains an H leveleven when output designating signal DOT is generated during the periodof delay column address strobe signal ZCASE being at an L level.

When output designating signal DOT attains an L level, the output ofinverter circuit 59 is brought to an H level, and precharge transistors60 a and 60 b are both turned on. Internal data bus lines 915 a and 915b are discharged to the level of ground potential for a predeterminedtime. Thus, when data is newly read out in the static column mode or anormal mode, internal data bus lines 915 a and 915 b can be prechargedto a predetermined potential of the ground potential level.

If the precharge operation on internal data bus lines 915 a and 915 b tothe level of the ground potential is to be carried out only in datareadout, a structure may be provided in which inverter circuit 59attains an operable state when an output from gate circuit 57 attains anH level. This structure can easily be realized by an AND circuitreceiving an output of gate circuit 57 and output designating signal DOTand by providing the output of this AND circuit to precharge transistors60 a and 60 b.

According to the above-described structure of the control circuit,output node 6 can be reliably precharged to the level of an intermediatepotential when data is to be newly read out regardless of whether data Hor L is previously read out.

The number of inverter circuits in delay circuits 15, 17, 19 and 12shown in FIG. 1 and delay circuit 61 shown in FIG. 5 are not limited tothose illustrated, and an appropriate number of stages providing anappropriate delay time can be used.

[Modification 1]

FIG. 7 shows a modification of the output circuit of the firstembodiment. In the structure shown in FIG. 7, an n channel MOStransistor 62 rendered conductive in response to an output of NANDcircuit 22 for driving output node 6 to the level of a referencepotential VREF of Vcc/2, for example, for a predetermined time isprovided. The output of NAND circuit 13 is provided to drive transistor2 b of a large driving capability via an inverter 63. In a dischargingoperation of output node 6 in the present structure, drive transistor 2a operates to gently discharge output node 6. Then, drive transistor 2 bis turned on at an elapse of a predetermined time period, whereby outputnode 6 is rapidly discharged to the level of a ground potential. Whenone readout operation is completed, or in the case where a signal of anL level is output following the output of an H level in static columnmode, transistor 62 conducts in response to an output of NAND circuit 22to drive output node 6 to the level of reference potential VREF. Outputnode 6 can be reliably driven to the intermediate potential of Vcc/2 byusing the potential level of Vcc/2 used in a dynamic semiconductormemory device as this reference potential VREF. In reading out data ofan H level and an L level, the data ascertain timing can be made tocoincide with each other without generating ringing, and high speedaccess can be realized. This is because the access time is determined bythe longer one of data ascertaining times of read out data H and L.

[Modification 2]

FIG. 8 shows another modification of the first embodiment. In FIG. 8, adelay circuit 15 b and an NOR 16 b are provided in order to generate asignal of an H level for a predetermined time in response to the fall ofthe potential of node N2. Delay circuit 15 b has a structure similar tothat of invert delay circuit 15 a for generating a one shot pulse inresponse to a fall of the potential of node N1. The outputs of NORcircuits 16 a and 16 b are provided to OR circuit 64. The output of ORcircuit 64 is provided to NAND circuit 22.

According to the structure shown in FIG. 8, a one shot pulse signal canbe generated at the fall of the potential of node N1 or N2 to turn onprecharge transistor 62 for a predetermined time. Therefore, regardlessof whether the data signal appearing on output node 6 attains an H levelor an L level, precharge transistor 62 is turned on to precharge theoutput node 6 to the level of intermediate potential VREF at thecompletion of one data readout cycle or when data is newly to be readout.

According to the first embodiment, an output node is driven to anintermediate potential at the completion of a data signal readoutoperation or when data is to be newly read out. Therefore, output node 6will be driven from the level of an intermediate potential to the levelof a corresponding logic level in newly providing a signal of an H or anL state, so that the potential amplitude of the output node can bereduced. Therefore, generation of ringing can be prevented, and a datasignal can be output stably and speedily. The time required to ascertainthe potential of the H and L levels can be reduced to allow high speedaccess since the output node is maintained at an intermediate potential.

Furthermore, power consumption in a data signal output operation can bereduced since the output node is driven to the potential level of H or Lfrom an intermediate potential level.

Embodiment 2

FIG. 9 shows a structure of an output circuit according to a secondembodiment of the present invention for discharging output node 6 to thelevel of ground potential.

Referring to FIG. 9, an output circuit includes an inverter circuit 5for inverting an internal readout data signal ZDD, an AND circuit 3 forreceiving output permission signal OEM and an output of inverter circuit5, and an AND circuit 4 for receiving output permission signal OEM andan internal readout data signal ZDD. Internal readout data signal ZDDhas a logic opposite to that of data DD.

The output circuit further includes a delay circuit 12 for delaying anoutput of AND circuit 4, i.e. a signal on node N2 for a predeterminedtime, a NAND circuit 13 for receiving the signal on node N2 and anoutput of delay circuit 12, an inverter circuit 64 for receiving anoutput of NAND circuit 13, and a p channel MOS transistor 67 responsiveto the signal potential on output node 6 for adjusting the “H” drivingcapability of inverter 64. Inverter circuit 64 includes a p channel MOStransistor 66 and an n channel MOS transistor 65 connected in acomplementary manner between transistor 67 and ground node. Transistor67 is provided between p channel MOS transistor 66 and the powerpotential node supplying a power supply potential Vcc, and receives atits gate a signal on output node 6.

The output circuit further includes an n channel MOS transistor 1responsive to an output of AND circuit 3 for charging output node 6 tothe level of power supply potential Vcc, an n channel MOS transistor(drive transistor) 2 a responsive to an output of AND circuit 4 fordischarging the potential of output node 6 in a relatively gentlemanner, and an n channel MOS transistor (drive transistor) 2 bresponsive to an output of inverter circuit 64 for discharging thepotential of output node 6 to the level of the ground potential. Thecurrent driving capability of transistor 2 a is set smaller than that oftransistor 2 b. The operation of the output circuit of FIG. 9 will nowbe described with reference to the operation waveform diagram of FIG.10.

The operation in a case where internal readout data signal ZDD is an Hlevel will be described. When output permission signal OEM attains an Llevel, the outputs of AND circuits 3 and 4 are both pulled down to an Llevel, and drive transistors 1, 2 a, and 2 b are turned off.

When output permission signal OEM is pulled up to an H level, the outputof AND circuit 4 is driven to an H level. As a result, drive transistor2 a is turned on, and output node 6 is discharged in a relatively gentlemanner.

The signal potential on output node 6 is provided to the gate oftransistor 67. Transistor 67 has its current driving capabilityincreased (a greater conductance) as the gate potential thereof isreduced. At an elapse of a predetermined time, the output of NANDcircuit 13 (the signal potential on node N3) attains an L level. Inresponse to the fall of the signal potential on node N3, the output ofinverter circuit 64 attains an H level. The potential level of thesignal output of an H level from inverter 64 varies according to thepotential level of output node 6.

The voltage transmitted to p channel MOS transistor 66 of invertercircuit 64 by transistor 67 is Vcc−V (6)−Vth, where V (6) is thepotential of output node 6 and Vth is the absolute value of thethreshold voltage of p channel MOS transistor 67. According to reductionin the potential of output node 6, the potential level of the H outputof inverter circuit 64 increases, whereby drive transistor 2 b is turnedon more deeply to discharge the potential of output node 6 to the levelof the ground potential at high speed. More specifically, the potentiallevel of the H output of inverter circuit 64 increases as the potentialof output node 6 is lowered, which causes drive transistor 2 b to beturned on more deeply. When the potential of output node 6 is reduced toa sufficient low level, drive transistor 2 b discharges output node 6 tothe level of ground potential more speedily. Since driver transistor 2 bdischarges output node 6 towards the level of the ground potential athigh speed when the potential of output node 6 arrives at a level whereno ringing occurs, an output signal can be generated stably with noringing.

A normally-on-transistor can be used for p channel MOS transistor 67,which serves as a resistance element having a resistance (conductance)reduced (increased) in proportion to reduction of the potential ofoutput node 6. In this case, when the output of inverter 64 is driven toan H level, the rise of the output potential of inverter 64 becomesfaster according to the fall of the potential of output node 6, so thatdrive transistor 2 b is turned on deeply according to the fall of thepotential of output node 6.

The operation waveform diagram of FIG. 10 represents the state where alldriver transistors 1, 2 a and 2 b are turned off when output node 6 isdischarged to the level of ground potential and output permission signalOEM attains an L level. It is to be noted that this output node 6driving circuitry of FIG. 9 may be used in a combination with thestructure as in the first embodiment where the potential at output node6 is maintained at the level of an intermediate potential. In FIG. 10,the potential change to the intermediate potential in output node 6 isshown as Q′. The advantages set forth in the foregoing can be obtainedby increasing the discharging force in proportion to reduction in thepotential when output node 6 is maintained at the intermediate level.

FIG. 11 shows an operation waveform where a valid readout data istransmitted after output permission signal OEM is rendered active. InFIG. 11, output node 6 is precharged to the level of intermediatepotential. Output node 6 is precharged to the intermediate potentialwhen output permission signal OEM attains an L level. When outputpermission signal OEM is driven to an H level and internal readout datasignal ZDD attains an L level, the potential of node N1 is driven to anH level, whereby the potential of output node 6 increases to result inoutput data Q′ of an H level. When valid data appears at an elapse of apredetermined time and internal readout data signal ZDD attains an Hlevel, the potential of node N2 is pulled up to an H level, and thepotential of node N1 is pulled down to an L level. As a result, drivetransistor 2 a is turned on, whereby output node 6 is gently dischargedtoward the level of ground potential.

Accordingly, the potential of output signal Q′ is gradually lowered.

When node N3 (output of NAND circuit 13) attains an L level at an elapseof a predetermined time, the output of inverter circuit 64 increasesgradually. The rising speed of the output of inverter circuit 64 dependsupon the potential of output nodes. When the potential of output signalQ′ is high, the output of inverter circuit 64 rises gently. When thepotential of output signal Q′ attains a sufficiently low level, theoutput of inverter circuit 60 rapidly rises to the level of power supplypotential Vcc. The driving capability of drive transistor 2 b is set toa great level when the potential of output node 6, i.e. the potential ofoutput signal Q′ attains a sufficiently low level, whereby output node 6is discharged speedily towards the level of ground potential. Therefore,in an operation where invalid data and then valid data are output, anoutput signal can be generated stably with no generation of ringing byadjusting the current driving capability of drive transistor 2 baccording to the potential level of output node 6 even when the logic ofthe valid data and the invalid data differ from each other.

The operation mode where invalid data appears on output node 6 will bedescribed in detail afterwards.

FIG. 12 shows a structure of the portion for driving output node 6 to anH level. In FIG. 12, drive transistor 1 a formed of an n channel MOStransistor conducting in response to a signal potential on node N1 and adrive transistor 1 b in parallel to drive transistor 1 a are provided todrive (charge) output node 6 to the level of power supply voltage Vcc inFIG. 12.

The control unit of the output circuit further includes a delay circuit12 a for delaying the signal potential on node N1 for a predeterminedtime, a NAND circuit 13 a for receiving a signal on node N1 and anoutput of delay circuit 12 a, a p channel MOS transistor 71 and an nchannel MOS transistor 73 having gates receiving the output of NANDcircuit 13 a, a p channel MOS transistor 72 provided between transistors71 and 73, an n channel MOS transistor 75 receiving a signal on outputnode 6 at its gate, and a p channel MOS transistor 74 provided betweentransistor 75 and a power potential supply node. The gate of transistor74 is connected to the node of transistors 72 and 73 and to the gate ofdrive transistor 1 b. The gate of transistor 72 is connected to the nodeof transistors 74 and 75. The operation of the circuit shown in FIG. 12will be now described with reference to the operation waveform diagramof FIG. 13.

It is assumed that internal readout data signal ZDD attains an L level.When output permission signal OEM attains an L level, the potential ofnodes N1 and N2 both attain an L level, and drive transistors 1 a and 2are both turned off. The output of NAND circuit 13 a attains an H levelsince the potential of node N1 attains an L level, and a signal of an Llevel is provided to drive transistor 1 b since transistor 73 is on.Therefore, drive transistor 1 b is also off.

When output permission signal OEM is driven to an H level, the potentialof node N1 is pulled up to an H level, and drive transistor 1 a isturned on. The current driving capability of drive transistor 1 a is setrelatively small, and the potential of output node 6 is increasedgently. The output of NAND circuit 13 a (output potential of node N3 a)is brought to an L level at an elapse of a predetermined time, wherebytransistor 73 is turned off and transistor 71 is turned on. Thepotential of output node 6 is provided to the gate of transistor 75.When the potential of output node 6 attains the level of an intermediatepotential, the current driving capability of transistor 5 is low (smallconductance), and the current driving capability of transistor 74 ishigh. Therefore, the gate potential of transistor 72 is relatively high,and the conductance of transistor 72 is low. Under this state, thepotential of drive transistor 1 b rises gently, and drive transistor 1 bhas its current driving capability restricted and charges output node 6in a relatively mild manner.

When the potential of output node 6 rises to a sufficiently high level,the current driving capability of drive transistor 75 is increased,which causes the gate potential of transistor 72 to be lowered to asufficient low level. The current driving capability of transistor 72becomes greater, whereby the potential of transistor 1 b increases athigh speed. The current driving capability thereof is increased tocharge output node at high speed. Here, the current driving capabilityof transistor 74 is set small according to increase of the gatepotential of transistor 1 b. The gate potential of transistor 72 isdischarged at high speed according to the increase in the potential ofoutput node 6. Transistor 72 is turned on deeply, which causes thecurrent driving capability of drive transistor 1 b to be increased athigh speed. Therefore, when the potential of output node 6 rises to alevel where no ringing is generated, the potential further increasesspeedily to generate an output signal stably with no ringing. In FIG.13, the operation waveform in the case where output node 6 is charged tothe level of intermediate potential is also indicated as output signalQ′.

As described above, the driving capability of an output node is adjustedaccording to the potential level thereof in accordance with thestructure of the output circuit of the second embodiment, so that thepotential of the output node attaining a potential level where ringingis not generated is driven speedily. Therefore, a stable output signalcan be generated with no generation of ringing.

Embodiment 3

In a dynamic semiconductor memory device with a static column modefunction, a column select operation is carried out according to anaddress transition detection signal φATD generated in response to achange in a column address signal. Column address strobe signal ZCAS isused only for the purpose of determining the timing of data output. Inthis case, there is a possibility that invalid data is generated at anoutput node according to the relationship of RAS-CAS delay time TRCD,i.e. the time required from activation of row address strobe signal ZRASto activation of column address strobe signal ZCAS, and columnaddress-CAS delay time TASC, i.e. the time required from a change incolumn address signal Ad to a change in column address strobe signalZCAS. Prior to description of the present third embodiment, theoperation where invalid data is output and invalid data is not outputwill be described with reference to the control signal generationcircuit of FIG. 5.

First, the operation in a case where invalid data is not output will bedescribed with reference to FIGS. 5 and 14.

When row address strobe signal ZRAS is activated to attain an L level, amemory cycle is initiated. The currently applied address signal Ad isentered as a row address signal X and row select operation is made. Inthis state, the control-circuit of FIG. 5 attains an initial state, andoutput permission signal OEM attains an L level.

When row address strobe signal ZRAS is activated to attain an L level,one shot pulse generation circuit 50 is enabled to provide an H leveloutput. Since column address buffer 907 is enabled in response to rowaddress strobe signal ZRAS in static column mode, the output of columnbuffer 907 does not change when row address signal X changes, so thatone shot address transition detection signal φATD is not generated(refer to FIG. 86). Alternatively, pulse transition detection circuit(ATD circuit) 920 may be adapted to attain an operable state when rowaddress strobe signal ZRAS attains an L level.

At an elapse of a row address hold time period, address signal Adchanges, and a column address signal Y is generated. In response tochange in address signal Ad, address transition detection signal φATD isactivated, whereby output designating signal DOT generated from one shotpulse generation circuit 50 attains an L level for a predetermined time.In response to the transition of output designating signal DOT to an Llevel, a pulse signal of an L level greater in period than that ofoutput designating signal DOT is applied to node N12 from one shot pulsegenerating circuit 52. The pulse width of the L level one shot pulsesignal applied on node N12 is greater than the L period of outputdesignating signal DOT by the delay time provided by delay circuit 61.

When the potential of node N12 attains an L level, a signal of an Hlevel is provided from NAND circuit 55 to node 13.

In a data reading operation, the output of gate circuit 57 attains an Hlevel.

In the initial state, the potential of node N14 attains an H level. Whenthe potential of node N13 attains an H level, the potential of node N15is pulled down to an L level. Thus, the potential at node of N14 isreliably set at the H level. Under this state, output permission signalOEM is still inactive at the L level.

When the address-CAS delay time TASC is long enough, delay columnaddress strobe signal ZCASE still attains an H level even when outputdesignating signal DOT is brought to an H level. Under this state, thepotential of node N14 is still at an H level. Therefore, when outputdesignating node DOT attains an H level, the potential of node N13 ispulled down to an L level, whereby the potential of node N15 is pulledup to an H level.

At an elapse of address-CAS delay time TACD, column address strobesignal ZCAS is activated to attain an L level, whereby delayed columnaddress strobe signal ZCASE attains an L level. In response to delayedcolumn address strobe signal ZCASE attaining an L level, a signal of anH level is provided from inverter circuit 54 onto node N11. Since thepotential of N15 is at an H level, the potential of node N14 is pulleddown to an L level in response to a rise of the potential of node N11,and output permission signal OEM attains an H level.

Valid data ZDD is already produced when output permission signal OEMattains an H level. In response to data signal ZDD, the potentials ofnodes N1 and N2 are driven to an L level and an H level, respectively.In response to the potential of node N2 attaining an H level, drivetransistor 2 a is turned on, whereby output Q is lowered gently. Then,drive transistor 2 b is turned on, and the potential of output Q islowered at high speed.

As described above invalid data is not output if time TAC is longenough. Output signal Q can change stably from the level of anintermediate potential, for example, to the level of ground potential orpower supply potential with no generation of ringing.

FIG. 15 shows an operation waveform in the case where invalid data isoutput. An output operation of invalid data will now be described withreference to FIGS. 15 and 5.

Row address strobe signal ZRAS is activated to attain an L level. Inresponse, output designating signal DOT is pulled to an H level. Inresponse to activation of internal row address strobe signal ZRAS, thecurrently applied address Ad is entered as a row address signal (Xaddress), and a row corresponding to this X address is selected.

At a change of address signal Ad, address transition detection signalφATD is generated. In response to address transition detection signalφATD, one shot pulse generation circuit 50 generates output designatingsignal DOT of one shot pulse signal of an L level at an elapse of apredetermined time period.

When a column address signal is generated, column address strobe signalZCAS is immediately pulled down to an L level. More specifically, theaddress-CAS delay time TASC is extremely short in this case. Delayedcolumn address strobe signal ZCASE attains an L level before outputdesignating signal DOT is driven to an L level. In response, node N11attains an H level. Since the potential of node N15 is at an H level,the output of NAND circuit NA1 (potential of node N14) is driven to an Llevel, and output permission signal OEM is driven to an H level. Validdata is output at an elapse of a predetermined time period from thedrive of output designating signal DOT to an L level, and internalreadout data ZDD is pulled up to an H level. Therefore, when outputpermission signal OEM attains an H level, invalid data is outputalready. The potential of output signal Q rises according to this “L”invalid data signal ZDD. Then, valid data appears, and output signal Qis lowered according to an “H” internal readout signal ZDD.

Thus, when data DD of an L level is provided as valid data followingprovision of data DD at “H” as invalid data, the potential amplitude isgreat even in the case where output signal Q is set at the intermediatepotential. It is considered that the potential of output node 6 is notlowered enough when drive transistor 2 b is turned on, resulting in thepossibility of generation of ringing in output signal Q. A structurewith which when there is no ringing even in the case where such invaliddata is output will be described. It is assumed that output signal Q isprecharged to an intermediate potential level in the followingdescription. Although the drive of output signal Q to an L level isdescribed, the same applies for output signal Q driven to an H level.

FIG. 16 shows a structure of an input circuit according to a thirdembodiment of the present invention. In FIG. 16, a structure is shownfor preventing generation of ringing when a data signal of an L level isoutput to output node 6. By providing a similar structure with respectto node N1 (output of NAND circuit 3), a structure of preventinggeneration of ringing in providing a data output signal of an H levelcan be realized.

Referring to FIG. 16, the output circuit includes, as basic components,an AND circuit 4 for receiving an output permission signal OEM andinternal readout data signal ZDD, an inverter circuit 5 for invertinginternal readout data signal ZDD, an AND circuit 3 for receiving anoutput of inverter circuit 5 and output permission signal OEM, a drivetransistor 1 responsive to an output of AND circuit 3 for chargingoutput node 6 to the level of power supply voltage Vcc, a drivetransistor 2 a of low current driving capability responsive to an outputof AND circuit 4 for gently discharging output node 6 to the level ofground potential, and a drive transistor 2 b provided in parallel todrive transistor 2 a for discharging output node 6 with a currentdriving capability greater than that of drive transistor 2 a.

The control system for controlling the operation of drive transistor 2 bincludes an inverter circuit 81 for inverting output designating signalDOT, an NAND circuit 82 for receiving a signal on node N2 (output of ANDcircuit 4) and an output of inverter circuit 81, and a flipflop 84 forreceiving an output of NAND circuit 82 and a signal on output node N2.Flipflop 84 includes cross-coupled NAND circuits NA3 and NA4. NANDcircuit NA3 has one input receiving an output of NAND circuit 82, andthe other input receiving an output of the NAND circuit NA4. NANDcircuit NA4 has one input receiving an output of NAND circuit NA3, andthe other input receiving a signal on node N2. Flipflop 84 has afunction to determine whether or not valid data appears on node N2.

The control system further includes an inverter circuit 85 for receivingan output of NAND circuit NA3 (signal on node N25) in flipflop 84, aNAND circuit 86 for receiving outputs of inverter circuit 85 and ANDcircuit 83, a delay circuit 87 for delaying an output of invertercircuit 85 for a predetermined time period, a delay circuit 84 fordelaying an output of NAND circuit 86, a NAND circuit 89 for receivingoutputs of delay circuits 87 and 88, and an AND circuit 90 for receivinga signal on node N2 and an output of NAND circuit 89. The output of ANDcircuit 90 is provided to the gate of transistor 2 b.

The delay time T1 of delay circuit 87 is set longer than delay time T2of delay circuit 88. The operation of the output circuit of FIG. 16 willbe is described with reference to the waveform diagram of FIG. 17.

The operation in a case where invalid data signal is provided will bedescribed with reference to FIG. 17A. Here, it is assumed that aninvalid data signal is data signal ZDD of an L level, and an valid datasignal is data signal ZDD of an H level.

When an invalid data signal is output, output permission signal OEMattains an H level, followed by output designating signal DOT attainingan inactive state of an L level. When output permission signal OEM ispulled up to an H level, the potential of node N2 attains an L levelaccording to invalid data signal ZDD. Under this state, drive transistor1 is turned on and drive transistor 2 a is turned off. Output node 6 ischarged to have the potential thereof increased via drive transistor 1.When output designating signal DOT is pulled down to an L level, asignal of an H level is provided from inverter 81 to node N23. Whenoutput designating signal DOT attains an L level, valid data appears,and internal readout data signal ZDD is pulled up to an H level. As aresult, the potential of node N2 is pulled to an H level, whereby drivetransistor 2 a is turned on and drive transistor 1 is turned off. Outputnode 6 is discharged gently.

When the potential of node N2 is pulled up to an H level, a signal of anL level is provided from NAND circuit 82 to node N24 since the potentialof node N23 is at an H level. When the potential of node N24 attains anL level, flipflop 84 is set, and the potential of node N25 attains an Hlevel (the potential of node N26 is at an H level). When node N25 risesto an H level, NAND circuit NA4 in flipflop 84 receives a signal of an Hlevel at both inputs, whereby the potential of node N26 is driven to anL level, and the potential of node N25 is fixed at an H level.

When the potential of node N25 is pulled up to an H level, the potentialof node N27 is pulled down to an L level. The output of AND circuit 83is at an L level since output designating signal DOT attains an L level.Therefore, when the potential of node N25 attains an H level, the outputof NAND circuit 86 is fixed at an H level.

At an elapse of a delay time T1 of delay circuit 87, NAND circuit 89receives a signal of an L level from delay circuit 87, and a signal ofan H level is provided on node N30. The potential of node N2 alreadyattains an H level, and therefore AND circuit 90 provides a signal of anH level on node N31, whereby drive transistor 2 b is turned on. As aresult, output node 6 is discharged at high speed via transistor 2 b.

As described above, output permission signal OEM is rendered activeprior to a change of output designating signal DOT when invalid data ispresent. In this case, the ON transition timing of output drivetransistor 2 b is determined by delay circuit 87 having a great delaytime. Thus, output node 6 is discharged at high speed via drivetransistor 2 b when the potential of output node 6 is low enough.Generation of a ringing can be reliably prevented even when invalid dataand valid data of different logics are output.

The operation in a case where an invalid data signal is not output willbe described with reference to FIG. 17B.

When invalid data is not output, output permission signal OEM attains anH level after output designating signal DOT is activated. As appreciatedfrom the circuit configuration of FIG. 5, output permission signal OEMis generated according to delayed column address strobe signal ZCASEwhen output designating signal DOT attains an H level.

Under this condition, when output permission signal OEM is brought to anH level, a readout data signal ZDD of an H level is already output, andthe potential of node N2 attains an H level in response to the rise ofthe potential of output permission signal OEM. When the potential ofnode N2 is pulled to an H level, output designating signal DOT isalready restored to an H level, and AND circuit 83 provides a signal ofan H level to node N28. In flipflop 84, node N26 is set to the initialstate of an H level, and node N25 is set to an initial state of an Llevel. Therefore, when the potential of node N2 attains an L level, thelatch state of flipflop 84 does not change even when output designatingsignal DOT is brought to an L level. Similarly, the output of NANDcircuit 82 attains an H level (the output of inverter circuit 81 isalready driven to an L level) when the potential of node N2 is pulled upto an H level from L level, so that the latch state of flipflop 84 doesnot change. Therefore, the potential of node N27 is fixed at an H level.

Under this state, when the potential of node N2 is pulled up to an Hlevel to cause the potential of node N28 to rise to an H level, thepotential of node N29 is pulled down to an L level by NAND circuit 86.At an elapse of a delay time of T2 of delay circuit 88, NAND circuit 89provide a signal of an H level to node N30. As a result, AND circuit 90provides a signal of an H level on node N31, and drive transistor 2 b isturned on.

Invalid data is not output when address access time TASC is relativelylong. In this case, activation of output enable signal OEM causes outputnode 6 to be gently discharged by drive transistor 2 a to result inreduction of the potential thereof since an invalid data signal is notoutput. At an elapse of delay time T2 of delay circuit 88, drivetransistor 2 b is turned on, whereby output node 6 is discharged to thelevel of ground potential at high speed. Since invalid data is notoutput here, drive transistor 2 b of a great current driving capabilityis activated after the potential of output node 6 is low enough.Therefore, a stable output signal with no ringing can be obtained.

In the operation waveform diagrams of FIGS. 17A and 17B, internalreadout data signal ZDD is set to an L level in a standby state. Similarto the first embodiment, a structure is employed where internal datalines 915 a and 915 b are both precharged to the level of groundpotential when the output node is maintained at the level of theintermediate potential.

The current driving capability of drive transistors 2 a and 2 b can beselected by differentiating the size of drive transistors 2 a and 2 b,i.e. the ratio of the gate width W to gate length L, and β (the constantproportional to W/L) of drive transistors 2 a and 2 b are to bedifferentiated.

It is not particularly necessary to differ the current drivingcapability of drive transistor 2 a from that of drive transistor 2 b.Since drive transistor 2 a is on when drive transistor 2 b is turned on,output node 6 is discharged via the two transistors, so that thecapability of discharging output node 6 is set to a great levelequivalently. A similar effect can be obtained even when the currentdriving capabilities of drive transistors 2 a and 2 b are the same.

Also, an effect similar to that of the above-described embodiment can beobtained even when three or more transistors for discharging output node6 are provided and the discharging operation of output node 6 is carriedout in several stages. Such a structure can easily be realized byproviding an additional delay circuit at the output of AND circuit 90 inthe structure of FIG. 16 and providing a transistor rendered conductivein response to an output of this delay circuit between output node 6 andthe ground potential node.

The number of stages of inverters in the delay circuit is arbitrary aslong as the condition that the delay time of delay circuit 88 is setshorter than that of delay circuit 87 is met. Furthermore, a delayelement different from an inverter (for example, a RC delay element) maybe used.

[Modification 1]

In FIG. 18A, delay circuits 87 and 88 shown in FIG. 16 are not providedin the output control unit of the present modification. NAND circuit 89receives signals from NAND circuit 86 and inverter circuit 85 shown inFIG. 16. The output of NAND circuit 89 is provided to AND circuit 90 ofFIG. 16.

Referring to FIG. 18A, NAND circuit 89 includes a p channel MOStransistor 890 provided between a power potential supply node and anoutput node 894 and receiving an output signal A from NAND circuit 86 atits gate, and a p channel MOS transistor 891 provided between the supplynode of the power supply potential and output node 894 and receiving anoutput signal B from inverter circuit 85 at its gate. The currentdriving capability of transistor 890 is set greater than that oftransistor 891.

NAND circuit 89 further includes an n channel MOS transistor 892receiving output signal A from NAND circuit 86 at its gate, and an nchannel MOS transistor 890 receiving output signal B from invertercircuit 85 at its gate. Transistors 892 and 893 are connected in seriesbetween output node 894 and the ground potential node. The signal C onoutput node 894 is provided to the next stage, or AND circuit 90. Thecurrent driving capability of transistors 892 and 893 are set to thesame level. The operation of the NAND circuit shown in FIG. 18A will nowbe described with reference to the operation waveform diagram of FIG.18B.

When output signal A from NAND circuit 86 attains an L level, p channelMOS transistor 890 is turned on. As a result, the potential of outputnode 894 is driven with a current driving capability relatively greaterthan that of transistor 890 to be pulled up to an H level at arelatively high speed.

When output signal B from inverter circuit 85 attains an L level, pchannel MOS transistor 891 is turned on. Output node 894 is charged at arelatively slow rate via transistor 891. The signal on output node 894AND circuit 90 at the next stage. When the signal potential on outputnode 894 exceeds the input logic threshold value of AND circuit 90, asignal of an H level is provided from AND circuit 90. Therefore, bysetting the current driving capability of transistors 890 and 891 atappropriate levels, the time required for the output of AND circuit 90to be pulled up to an H level can be set identical to the delay timeprovided by delay circuits 87 and 88 of FIG. 16, as shown in FIG. 18B.

[Modification 2]

FIG. 19 shows a structure of a control unit of an output circuitaccording to a second modification of the third embodiment. Referring toFIG. 19, a control unit includes gate circuits 91 and 92 each receivingoutput permission signal DOT and output designating signal OEM, aflipflop 93 set in response to a rise of the output of gate circuit 91,a flipflop 94 sets in response to a rise of the output of gate circuit92, a delay circuit 95 for delaying a signal on node N2 for apredetermined time, an AND circuit 96 receiving outputs of delay circuit95 and flipflop 93, an AND circuit 97 receiving an Q output of flipflop94 and an output of delay circuit 95, an AND circuit 98 receiving asignal on node N2 and an output of AND circuit 96, an AND circuit 99receiving a signal on node N2 and an output of AND circuit 97, a drivetransistor 2 ba responsive to an output of AND circuit 98 fordischarging output node 6 to the level of ground potential, and a drivetransistor 2 bb responsive to an output of AND circuit 99 fordischarging output node 6 to the level of ground potential.

Gate circuit 91 provides a signal of an H level when signals DOT and OEMboth attain an L level. The case where output designating signal DOT isdriven to an L level when output permission signal OEM is at an L levelis the case where invalid data is not output as shown in FIG. 17B. Undersuch a condition, gate circuit 91 provides a signal of an H level to setflipflop 93, and a signal of an H level is output from the Q output offlipflop 93.

Gate circuit 92 provides a signal of an H level when output designatingsignal DOT attains an L level during the period of output permissionsignal OEM being at an H level. Output designating signal DOT attains anL level when output permission signal OEM is high in the case where aninvalid data signal is output. In this case, gate circuit 92 provides asignal of an H level, and flipflop 94 is set. A signal of an H level isprovided from the Q output of flipflop 94.

The operation will be described briefly. When the potential on outputnode N2 attains an H level, drive transistor 2 a is turned on, wherebyoutput node 6 is discharged gently. At an elapse of a predeterminedtime, the output of delay circuit 95 is driven to an H level. When thereis a possibility of an invalid data output, flipflop 94 is set by gatecircuit 92, to provide a signal of an H level from the Q output thereof.When there is no possibility of an invalid data output, flipflop 93 isset by gate circuit 91, whereby a signal of an H level is provided fromthe Q output thereof.

When the output of delay circuit 95 attains an H level, one output ofAND circuits 96 and 97 attains an H level. In response, one output ofAND circuits 98 and 99 attains an H level.

The current driving capability of drive transistor 2 ba is set greaterthan that of drive transistor 2 bb. Therefore, when no invalid data isoutput, drive transistor 2 ba is turned on by flipflop 93 and ANDcircuits 96 and 98, whereby the potential of output node 6 is dischargedat a high speed. When invalid data is not output, the potential ofoutput node 6 is already discharged by drive transistor 2 a, so that anoutput signal can be generated stably without ringing even when outputnode 6 is discharged with a great current driving capability.

When there is a possibility of invalid data being output, drivetransistor 2 bb is turned on via flipflop 94, and AND circuits 97 and99. In this case, it can be considered that the potential of output node6 is not low enough. Therefore, output node 6 is discharged gently bydrive transistor 2 bb having a relatively small driving capability.Since drive transistors 2 a and 2 bb both are turned on, output node 6is discharged at a rate higher than that of driving output node 6 withone drive transistor. Therefore, an output signal can be generatedstably with no generation of ringing.

In a static column operation mode, output designating signal DOT attainsan L level when signal OEM is high. When there is a possibility thatinvalid data is output first, flipflop 93 is set continuously duringthis static column operation mode. Flipflops 93 and 94 are reset inresponse to a fall of output permission signal OEM. In a static columnmode, it can be considered that flipflops 93, and 94 are both set anddrive transistors 2 ba and 2 bb are both turned on. However, as shown inthe first embodiment, output node 6 is temporarily set at anintermediate potential after completion of a data signal output in astatic column mode. Therefore, there is no possibility of generation ofringing even when all drive transistors 2 a, 2 ba and 2 bb are turnedon.

Here, flipflops 93 and 94 may be formed so as to be reset by addresstransition detection signal φATD. In this case, an inverted signal ofoutput signal OEM and address transition detection signal φATD are ORed,and the ORed output is supplied to the reset inputs of flip-flops 93 and94. When flipflops 93 and 94 are reset according to column addresstransition detection signal φATD, flipflop 94 is set to effectdischarging of output node 6 by drive transistors 2 a and 2 bb in astatic column mode operation.

Since output node 6 is discharged from the level of intermediatepotential to the ground potential, output node 6 can be discharged tothe level of ground potential at a sufficient high speed even whendriven only by two drive transistors 2 and 2 bb.

According to the structure shown in FIG. 19, a similar effect can beobtained by a structure in which AND circuit 96 receives output signalsof delay circuits 95 and NAND circuit 86, and AND circuit 97 receivesoutput signals of delay circuit 95 and inverter 85 (refer to FIG. 16).

[Modification 3]

As for a third modification of an output circuit according to the thirdembodiment, the portion of NAND circuit 89 and delay circuits 87 a and88 of FIG. 16 are shown in FIG. 20. Referring to FIG. 20, delay circuit87 a includes a delay circuit 87 a for delaying a signal received frominverter 85 at node N27, and a delay circuit 88 for delaying a signal atnode N29 (output of NAND circuit 86) for a predetermined time. Delaycircuit 87 a includes cascaded three stages of inverter circuits871-873, and a gate circuit 874 having one input receiving an output ofdelay circuit 88 and the other input receiving an output of invertercircuit 873. Gate circuit 874 provides a signal of an H level when theoutput of inverter circuit 873 attains an L level and the output ofdelay circuit 88 attains an H level. The outputs of delay circuits 87 aand 88 are provided to NAND circuit 89. The output of NAND circuit 89 isapplied to AND circuit 90.

AND circuit 90 turns on drive transistor 2 b when the potential on nodeN2 attains an H level and the output of NAND circuit 89 attains an Hlevel.

FIG. 21 shows a structure of NAND circuit 89 of FIG. 20. Referring toFIG. 21, NAND circuit 89 includes p channel MOS transistors 89 a and 89c for receiving a signal potential on node N40 at their gates, and a pchannel MOS transistor 89 b and an n channel MOS transistor 89 d forreceiving a signal potential on node N41 at their gates. Transistors 89a and 89 b are connected in parallel between the power supply potentialnode and output node N30. Transistors 89 c and 89 d are connected inseries between output node N30 and the ground potential node.Transistors 89 a and 89 b may have the same size. Alternatively, thesize (channel width) of transistor 89 b may be set greater than that oftransistor 89 a. The operation of the circuit shown in FIGS. 20 and 21will now be described with reference to the operation waveform diagramof FIG. 22.

When an invalid output is present, the potential level of node N29attains an H level, which causes the signal potential on node N41 to bedriven to an H level. In this case, gate circuit 874 in delay circuit 87a functions as an inverter circuit. Therefore, when the signal potentialon node N27 attains an L level, the potential of node N40 attains an Llevel at an elapse of a predetermined time. NAND circuit 89 has only toturn on p channel MOS transistor 89 a, whereby output node N30 ischarged via transistor 89 a only as shown in FIG. 21.

Therefore, the potential rise of node N30 is relatively gentle. When thepotential level of node N30 exceeds the input logic threshold voltage ofAND circuit 90, the output of (potential of node N31) AND circuit 90attains an H level since the potential of node N2 attains an H level.

When an invalid output is absent, the potential on node N27 attains an Hlevel, and gate circuit 874 functions as a buffer circuit. When thepotential of node N29 attains an L level, the potential on node N21 isdriven to an L level at an elapse of a predetermined time period bydelay circuit 88, whereby the output of gate circuit 874 attains an Llevel. In NAND circuit 89, p channel MOS transistors 89 a and 89 b areboth turned on to charge output node N30. When the potential of node N30exceeds the input logic threshold AND circuit 90, a signal of an H levelis provided on node N31 by AND circuit 90.

The rise of the signal potential on node N30 is relatively gentle whenthere is an invalid output, and relatively speeded up when there is noinvalid output. As a result, the rising time of the signal potential onnode N31 can be differentiated, and the ON-timing of output drivetransistor 2 b can be made different between when there is an invalidoutput and when there is not an invalid input. If the input/outputresponse characteristic of AND circuit 90 is relatively gentle, the riseof the signal potential on node N31 follows that of node N30. Outputdrive transistor 2 b is increased gradually in driving capability whenthere is an invalid output, and increased rapidly when there is noinvalid output. Thus, output node 6 can be discharged at high speed whenthere is no possibility of generation of ringing.

Embodiment 4

FIG. 23 shows a structure of a control unit of an output circuitaccording to a fourth embodiment for discharging an output signal Q tothe level of ground potential.

Referring to FIG. 23, an output circuit includes an AND circuit 3receiving output permission signal OEM and an output of inverter circuit5 that receives internal readout data signal ZDD, an AND circuit 4receiving internal readout data signal ZDD and output permission signalOEM, a drive transistor 1 rendered conductive in response to an outputof AND circuit 3 for driving output node 6 to the level of power supplypotential Vcc, a drive transistor 2 a responsive to an output of ANDcircuit 4 for discharging output node 6 to the level of groundpotential, and a drive transistor 2 b provided in parallel to drivetransistor 2 a, and responsive to a control signal from control circuit100 for discharging output node 6 to the level of ground potential.

Control circuit 100 includes an inverter circuit 81 for inverting thelogic of a signal on node N2 (output of AND circuit 4), an AND circuit101 for receiving a signal potential on node N2 and an output ofinverter circuit 81, an inverter circuit 102 for inverting the logic ofoutput designating signal DOT, an NAND circuit 103 for receiving outputsof AND circuit 101 and inverter circuit 102, an NAND circuit 104 forreceiving an output of AND circuit 101 and output designating signalDOT, a latch circuit 105 for receiving an output of NAND circuit 103 andsignal on node N2, and a latch circuit 106 for receiving an output ofNAND circuit 104 and a signal on node N2.

Latch circuit 105 includes an NAND circuit NA5 for receiving an outputof NAND circuit 103 at one input, and an NAND circuit NA6 for receivinga signal on node N2 at one input. The output of NAND circuit NA6 isprovided to the other output of NAND circuit NA5. The output of NANDcircuit NA5 is provided to the other input of NAND circuit NA6. Latchcircuit 106 similarly includes cross-coupled NAND circuits NA7 and NA8.NAND circuit NA7 receives the output of NAND circuit 104 at one inputand the output of NAND circuit NAB at the other input. NAND circuit NA8receives a signal on node N2 at one input and an output of NAND circuitNA7 at the other input.

Output control circuit 100 further includes a delay stage 107 fordelaying an output of NAND circuit NA5 of flipflop 105 (signal on nodeN46) for a predetermined time and inverting a logic thereof, a delaycircuit 108 for delaying an output of NAND circuit NA7 of flipflop 106for a predetermined time and inverting the logic thereof, an NANDcircuit 89 for receiving outputs of delay circuits 107 and 108, and anAND circuit 90 for receiving a signal on node N2 and an output of NANDcircuit 89. The output of AND circuit 90 is applied to the gate of drivetransistor 2 b.

The delay time of delay circuit 107 is set longer than that of delaycircuit 108. The operation of the circuit of FIG. 23 will now bedescribed with reference to the operation waveform diagrams of the FIGS.24A and 24B.

The operation in a case where an invalid data signal is output will bedescribed with reference to FIG. 24A. Here, an invalid data signal is atan L level and a valid data signal is at an H level. At the initialstate, output permission signal OEM is at an L level, and outputdesignating signal DOT is at an H level. Internal readout data signalZDD maintains an L level even when output permission signal OEM ispulled up to an H level, and node N2 maintains an L level.

In this state, in response to output designating signal DOT driven to anL level, inverter circuit 102 drives potential of node N43 to an Hlevel, and NAND circuit 103 functions as an inverter during this period.The output of NAND circuit 104 maintains the state of an H level sincethe output of AND circuit 101 is at an L level.

When a valid data signal ZDD is applied to internal data bus line 915 b,the potential of node N2 is driven to an H level. This causes the outputof inverter circuit 81 to be pulled down to an L level, whereby a pulsesignal of an H level having a time width of the delay time of invertercircuit 81 is generated from AND circuit 101.

In response to a one shot pulse signal from AND circuit 101, NANDcircuit 103 generates a one shot pulse signal of an L level on node N45.As a result, the output of NAND circuit NA5 is driven to an H level, andthe potential of node N46 is set to an H level in latch circuit 105.

Output designating signal DOT attains an L level and the latching stateof latch circuit 106 does not change (output of NAND circuit 104maintains an H level) even when a one shot pulse signal of an H level isgenerated on node N44. More specifically, node N49 (output of NANDcircuit NA7 of latch circuit 106) is fixed at an L level. The output ofdelay circuit 108 attains an H level, and NAND circuit 89 functions asan inverter circuit.

At an elapse of the delay time of delay circuit 107, a signal of an Llevel is provided from delay circuit 107 to drive the output of NANDcircuit 89 to an H level. Then, the output of AND circuit (signalpotential on node N31) attains an H level since the potential of node N2already attains an H level. Therefore, drive transistor 2 b is turnedon.

More specifically, when an invalid data signal is output, drivetransistor 2 b is turned on at an elapse of a delay time T1 of delaycircuit 107 from the time of drive transistor 2 a being turned on. As aresult, when the invalid data signal and the valid data signal differ inlogic, drive transistor 2 b is turned on when the potential of outputnode 6 reaches a sufficient low level where no ringing is generated.

The operation in the case where an invalid data signal is not outputwill be described with reference to FIG. 24B. In this state, outputdesignating signal DOT first attains an L level for a predetermined timeperiod. In response to this output designating signal DOT, the output ofinverter circuit 102 is pulled up to an H level for a predetermined timeperiod. However, the potential of node N2 is at an L level, and theoutput of AND circuit 101 is at L level yet. Therefore, the outputs ofNAND circuits 103 and 104 maintain a level of the H level.

During the period of output designating signal DOT being at an L level,valid data is provided on internal data bus line 915 b, and internaldata signal ZDD attains an H level. Output permission signal OEM attainsan H level after output designating signal DOT is pulled up to an Hlevel, and the potential of node N2 attains an H level.

In response to a rise of the potential of node N2, a one shot pulsesignal of an H level is generated from AND circuit 101 on node N44.Output designating signal DOT is already restored to an H level, and theoutput of inverter circuit 102 attains an L level. Therefore, the outputof NAND circuit 103 maintains an H level.

NAND circuit 104 responds to a one shot pulse signal of an H level fromAND circuit 101 to generate a pulse signal of an L level. As a result,output of NAND circuit NA7 of latch circuit 106 is pulled up to an Hlevel from an L level. In response to the transition of the output ofNAND circuit NA7 (signal potential on node N49) to an H level, theoutput of NAND circuit NA8 is driven to an L level, and the potential ofnode N49 is latched to L level.

At an elapse of a delay time T2 of delay circuit 108, the output ofdelay circuit 108 is pulled up to an H level.

The potential of node N46 attains an L level, and the output of delaycircuit 107 attains an H level. Therefore, in response to an output ofdelay circuit 108, the output of NAND circuit 89 is pulled to an Hlevel. Then, the output of AND circuit 90 is pulled up to an H level.Drive transistor 2 b is rendered conductive in response to an output ofAND circuit 90, whereby output node 6 is discharged to the level ofground potential. As described above, when no invalid data signal isoutput, drive transistor 2 b is turned on at an elapse of a delay timeof delay circuit 108. The delay time of delay circuit 108 is shorterthan that of delay circuit 107. Therefore, when an invalid data signalis not output, drive transistor 2 b can be turned on at an advancedtiming.

By adjusting the on-timing of drive transistor 2 b, generating ofringing can be reliably prevented.

It is to be noted that various modifications similar to those of theprior Embodiment 1 can be carried out under the structure shown in FIG.23. In the modification set forth in the following, a circuitconfiguration for pulling up the potential of output node 6 may beemployed, and the number of stages of inverters in a delay circuit maybe set to an arbitrary number.

[Modification 1]

FIG. 25 shows a circuit configuration for preventing generating ofringing during discharging of output node 6. Referring to FIG. 25, acontrol circuit 100 includes an inverter circuit 110 for inverting asignal potential on node N2, an AND circuit 111 for receiving a signalon node N2 and an output of inverter circuit 110, an inverter circuit112 for receiving output designating signal DOT, an NAND circuit 113 forreceiving outputs of AND circuit 111 and inverter circuit 112, a delaycircuit 118 a for delaying an output of NAND circuit 113 for apredetermined time period of T1, an NAND circuit 114 for receiving anoutput of AND circuit 111 and output designating signal DOT, a delaycircuit 118 b for delaying an output of NAND circuit 114 for apredetermined time period T2 (T2<T1), an NAND circuit 115 for receivingoutputs of delay circuits 118 a and 118 b, an inverter circuit 116 forinverting an output of NAND circuit 115, and a latch circuit 117 forreceiving an output of inverter circuit 116 and a signal on node N2.

Latch circuit 117 includes cross-coupled NAND circuits NA9 and NA10.NAND circuit NA10 provides a signal for driving drive transistor 2 b.NAND circuit NA9 receives a signal potential on node N2 at one input.NAND circuit N10 receives an output of inverter circuit 116 at oneinput. NAND circuits NA9 and NA10 have their outputs and the otherinputs cross-coupled. The operation of the circuit of FIG. 25 will bedescribed with reference to the operation waveform diagrams of FIGS. 26Aand 26B.

An operation in a case where an invalid data signal is output will bedescribed with reference to FIG. 26A. First, output designating signalOEM is pulled up to an H level. Here, readout data signal ZDD is at an Llevel which is an invalid data signal. The potential of node N2 and theoutput of AND circuit 111 are both at an L level, and the outputs ofNAND circuits 113 and 114 are at an H level. NAND circuit 115 provides asignal of an L level according to the outputs of delay circuits 118 aand 118 b, and inverter circuit 116 provides a signal of an H level. Thesignal potential of node N2 is at an L level, and the outputs of NANDcircuits NA9 and NA10 in latch circuit 117 are at an H level and an Llevel, respectively.

In response to output designating signal DOT at an L level for apredetermined time, the output of inverter circuit 112 is pulled to an Hlevel. During this period of output designating signal DOT being at an Llevel, a valid data signal is read out, and internal readout data signalZDD is driven to an H level. In response, the potential of node N2 ispulled to an H level. In response to a rise of the potential of node N2,a one shot pulse signal of an H level is generated on node N74 by a oneshot pulse signal generation circuit formed of AND circuit 111 andinverter circuit 110. NAND circuit 113 receives a signal of an H levelat one input via inverter circuit 112. Therefore, a signal of an L levelis transmitted onto node N75 in response to a rise of an output of ANDcircuit 111.

Since output designating signal DOT is at an L level, NAND circuit 114does not respond to a one shot pulse signal from AND circuit 111, andprovides a signal of an H level.

At an elapse of a predetermined time period T1 of delay circuit 118 a,the output of delay circuit 118 a is pulled down to an L level, and theoutput of NAND circuit 115 is pulled up to an H level (output of delaycircuit 118 b is high). In response to an output of NAND circuit 115, aone shot pulse signal of an L level is provided from inverter circuit116 on node N77. Thus, NAND circuit NA10 provides a signal of an Hlevel, whereby drive transistor 2 b is turned on.

NAND circuit NA9 responds to the signal of an H level generated fromNAND circuit NA10 in response to the one shot pulse signal to provide asignal of an L level even when the output of inverter circuit 116 isrestored to an H level. Therefore, NAND circuit NA10 maintains itsoutput at H level even when the output of inverter circuit 116 isrestored to an H level.

In response to the potential of node N2 attaining an L level, the outputof NAND circuit NA9 provides an output of an H level and NAND circuitNA10 receives a signal of an H level at both inputs, so that latchcircuit 117 supplies a signal of an L level. Therefore, drive transistor2 b is turned off.

As described above, when an invalid data signal is output, the ON-timingof drive transistor 2 b is determined by delay circuit 114 with a longerdelay time.

A discharge operation of output node 6 when an invalid data is notoutput will be described with reference to FIG. 26B.

First, output designating signal DOT attains an L level, and invertercircuit 116 provides an output of an H level. The signal potential ofnode N2 is still at an L level and the output of AND circuit 111 is atan L level. The output of NAND circuit 114 maintains the H levelregardless of a change in output designating signal DOT. Under thisstate, delay circuits 118 a and 118 b both provide outputs of an Hlevel. The outputs of NAND circuit 115, inverter circuit 116 and NANDcircuit NA10 are at an L level, an H level, and an L level,respectively.

A valid data signal is provided on internal data bus line 915 b, wherebyinternal data bus ZDD is pulled up to an H level. Then, outputpermission signal OEM is driven to an H level, and the potential of nodeN2 is pulled up to an H level. In response to the rise of the signalpotential on node N2, a one shot pulse signal of an H level is providedfrom AND circuit 111. Here, output designating signal DOT attains an Hlevel, and the output of inverter circuit 112 attains an L level.Therefore, the output of NAND circuit 113 exhibits no change and is heldat an H level. A one shot signal of an L level is provided from NANDcircuit 114 onto node N76. At an elapse of a delay time T2 of delaycircuit 118 b, the outputs of delay circuit 118 b and NAND circuit 115attain an L level and an H level, respectively. In response, the outputof inverter circuit 116 attains an L level, and NAND circuit NA10provides a signal of an H level on node N78. In response to a signal ofan H level on node N78, drive transistor 2 b is turned on.

Therefore, in the case where an invalid data signal is not output, thetiming at which drive transistor 2 b is turned on is determined by thedelay time of delay circuit 118 b. When an invalid data signal is notoutput, the potential of the output node is already low enough whendrive transistor 2 b is turned on. Therefore, a signal of an L level canbe output stably with no ringing.

Different variations can be applied to the modification of FIG. 25.

[Modification 2]

FIG. 27 shows a structure of an output circuit control unit according toa second modification of the fourth embodiment. Referring to FIG. 27,output control circuit 100 includes an NAND circuit 121 for receivinginternal readout data signal ZDD, an output of inverter circuit 5, andoutput permission signal OEM, and a latch circuit 122 for receivingoutput permission signal OEM and an output of NAND circuit 121. Latchcircuit 122 includes NAND circuits NA11 and NA12. NAND circuit NA11receives output permission signal OEM at one input and an output of

NAND circuit NA12 at the other input. NAND circuit NA12 receives anoutput of NAND circuit 121 at one input and an output of NAND circuitNA11 at the other input.

Output control circuit 100 further includes an inverter circuit 124 forreceiving an output of NAND circuit NA12 of latch circuit 122, a delaycircuit 123 for delaying a signal on node N2 for a predetermined time,an NAND circuit 126 for receiving outputs of inverter circuit 124 anddelay circuit 123, a delay circuit 125 for delaying an output ofinverter circuit 124 for a predetermined time period T4, an NAND circuit89 for receiving outputs of NAND circuit 126 and delay circuit 125, anAND circuit 90 for receiving an output of NAND circuit 89 and a signalon node N2. A drive control signal is provided from AND circuit 90 todrive transistor 2 b. An operation of the output control unit of FIG. 27will be described with reference to the operation waveform diagrams ofFIGS. 28A and 28B. In the output control circuit of FIG. 27, outputdesignating signal DOT is not used.

The operation in a case where an invalid output is present will bedescribed with reference to FIG. 28A. When an invalid data signal isoutput, output permission signal OEM is pulled up to an H level prior tointernal readout data signal ZDD. When internal readout data signal ZDDattains an H level during the H period of output permission signal OEM,the potential of node N2 is pulled up to an H level via AND circuit 4.

The output of inverter circuit 5 is at an H level according to the delaytime thereof even when internal readout data signal ZDD is pulled up toan H level. Therefore, all the three inputs of NAND circuit 121 attainsan H level, whereby a signal of an L level is output during the delaytime period of inverter circuit 5.

When a signal of an L level is provided to node N82 from NAND circuit121, the output of NAND circuit NA12 in latch circuit 122 attains an Hlevel. In response to a signal of an H level provided from NAND circuitNA12 to node 84, the output of NAND circuit NA11 attains an L level.Output node N84 of latch circuit 122 maintains an H level during thetime period of output permission signal OEM being at an H level.

When the potential on node N84 is pulled to an H level, the potential ofnode N85 is pulled down to an L level by inverter circuit 124. Theoutput of delay circuit 123 attains an L level prior to pull down of theoutput of inverter circuit 124 to an L level. When the output of delaycircuit 123 attains an H level in response to a rise of node N2, thepotential of node N85 already attains an H level. Therefore, the outputof NAND circuit 126 is fixed to an H level.

When the signal of an L level on node N85 is transmitted to one input ofNAND circuit 89 via delay circuit 125, a signal of an H level isprovided on node N30 from NAND circuit 89. In response, a signal of an Hlevel is provided from AND circuit 90 to node N31, whereby drivetransistor 2 b is turned on. More specifically, in the case where aninvalid data signal is output, drive transistor 2 b is turned on at atiming determined by delay time T4 of delay circuit 125. The delay timeof delay circuit 125 is set longer than delay time T3 of delay circuit123. Therefore, drive transistor 2 b is turned on after the potential ofoutput node 6 is pulled down to a sufficient low level, so thatgeneration of ringing can be prevented effectively.

The operation in a case where an invalid data signal is not output willbe described with reference to FIGS. 28A and 28B. In this case, outputpermission signal OEM attains an H level after internal readout data ZDDis pulled up to an H level. The output of inverter circuit 5 alreadyattains an L level, and therefore the output of NAND circuit 121 attainsan H level, when output permission signal OEM is pulled up to an Hlevel. Even when internal readout data signal ZDD is driven to an Hlevel from an L level, output permission signal OEM attains an L levelat that timing. Therefore, a signal of an H level is normally providedfrom NAND circuit 121.

A rise in output permission signal OEM causes the potential of node N2to be driven to an H level. When NAND circuit 121 provides an output ofan H level and output permission signal OEM attains an L level, NANDcircuit NA11 provides a signal of an L level and NAND circuit NA12provides a signal of an H level in latch circuit 122. Therefore, evenwhen output permission signal OEM is pulled up to an H level, thepotential of node N84 maintains an L level, and the output of NANDcircuit NA11 is fixed at an H level. More specifically, the potential ofnode N84 is fixed at an L level, and the potential of node N85 is fixedat an H level.

At an elapse of delay time T3 of delay circuit 123 following the rise ofthe potential of node N2 to an H level from an L level, the output ofdelay circuit 123 attains an H level and the output of NAND circuit 126attains an L level. Although the output of delay circuit 125 is fixed atan H level, the output of NAND circuit 89 is pulled up to an H level inresponse to a signal of an L level provided to node N86 from NANDcircuit 126. In response, the output of AND circuit 90 is pulled up toan H level. More specifically, in the case where an invalid data signalis not output, the ON-timing of drive transistor 2 b is determinedaccording to delay time T3 of delay circuit 123. Although drivetransistor 2 b is turned on in a relatively short period from an outputof a valid data signal, output node 6 is discharged from an intermediatepotential, for example, so that the potential level thereof issufficiently low. Therefore, a stable output signal is provided with noringing even when drive transistor 2 b is turned on.

Similar to the first modification, a structure for pulling up an outputsignal may be employed in the output control circuit of the secondmodification shown in FIG. 27. Furthermore, other similar changes may beemployed.

[Modification 3]

FIG. 29 shows a structure of a third modification of the fourthembodiment. In FIG. 29, a structure of an output control circuit fordischarging output node 6 to the level of ground potential is shown.

Referring to FIG. 29, output control circuit 100 includes an NANDcircuit 130 for receiving output permission signal OEM, internal readoutdata signal ZDD, and an output of inverter circuit 5, a delay circuit131 for delaying a signal potential on node N2 for a predetermined time,and a latch circuit 132 for receiving output permission signal OEM andan output of NAND circuit 130. Latch circuit 132 includes cross-coupledNAND circuits NA13 and NA14. NAND circuit NA13 has one input receivingoutput permission signal OEM and the other input receiving an output ofNAND circuit N14. NAND circuit NA14 has one input receiving an output ofNAND circuit 130 and the other input receiving an output of NAND circuitN13.

Output control circuit 100 further includes an NAND circuit 134 forreceiving an output of delay circuit 131 and an output of NAND circuitNA14 in latch circuit 132, an inverter circuit 133 for receiving anoutput from latch circuit 132 to node N95; an NAND circuit 135 forreceiving outputs of inverter circuit 133 and delay circuit 131, a delaycircuit 136 for delaying an output of NAND circuit 134 for apredetermined time period T1, a delay circuit 137 for delaying an outputof NAND circuit 135 for a predetermined time period T2, an NAND circuit136 for receiving outputs of delay circuits 136 and 137, and an ANDcircuit 90 for receiving an output of NAND circuit 89 and a signalpotential on node N2. A signal is provided from AND circuit 90 to thegate of drive transistor 2 b. The operation of the output controlcircuit of FIG. 29 will be described with reference to the operationwaveform diagrams of FIGS. 30A and 30B.

An operation in the case where there is an invalid data signal outputwill first be described with reference to FIG. 30A. When internalreadout data signal ZDD is at an L level, output permission signal OEMis pulled to an H level. In this state, the output of NAND circuit 130(signal potential on node N92) attains an H level.

When a valid data signal is transmitted and internal readout data signalZDD is pulled up to an H level, the potential of node N2 is driven to anH level. Responsively, NAND circuit 130 provides a one shot signal of anL level according to the delay time of inverter circuit 5. As a result,the output of NAND circuit NA14 is pulled up to an H level, and thesignals of both inputs of NAND circuit NA13 attain an H level in latchcircuit 132. Therefore, the potential of node N94 is pulled down to an Llevel. The latch state of latch circuit 132 is maintained during thetime period of output permission signal OEM being at an H level.

At an elapse of a delay time of delay circuit 131 following the rise ofthe potential of node N2 to an H level, the potential of node N93 ispulled up to an H level. The potential of node N95 attains an H level,and a signal of an L level is provided on node N97 from NAND circuit134.

In contrast, NAND circuit 135 maintains the output at the H level sincethe potential of node N96 is set to an L level by inverter circuit 133.Therefore, the output of delay circuit 137 demonstrates no change and ismaintained at the state of H.

At an elapse of a delay time T1 of delay circuit 136, the output ofdelay circuit 136 is pulled up to an L level, and a signal of an H levelis provided from NAND circuit 89 to node N30. As a result, the output ofAND circuit 90 attains an H level (the potential of node N2 alreadyattains an H level). In response to a signal of an H level on node N31,drive transistor 2 b is turned on to discharge output node 6 at highspeed.

An operation in the case where an invalid data signal is not output willbe described with reference to FIG. 30B. In this case, output permissionsignal OEM is driven to an H level after internal readout data signalZDD attains an H level. Therefore, the output of NAND circuit 130 isfixed at an H level, whereby latch circuit 130 maintains the initialstate. Since latch circuit 132 has reset by an output permission signalOEM of an L level at the initial state, NAND circuit NA14 provides asignal of an L level to node N95. Therefore, a signal of an H level isconstantly provided from inverter circuit 133 onto node N96.

At an elapse of a delay time of delay circuit 131 from the rise of thepotential of node N92 to an H level, the potential of node N93 is pulledto an H level. The potential of node N95 attains an L level, and thepotential of node N96 attains an H level. Therefore, when the potentialof node N93 is pulled up to an H level, a signal of an L level isprovided from NAND circuit 135 to node N98. At an elapse of delay timeT2 of delay circuit 137, the output of delay circuit 137 is pulled up toan H level. As a result, a signal of an H level is provided from NANDcircuit 89 to node N30, and a signal of an H level is provided on nodeN31 by AND circuit 90, and drive transistor 2 b is turned on.

When there is a possibility of an output of an invalid data signal, theON-timing of drive transistor 2 b is determined by the delay time ofdelay circuits 131 and 136. In the case where no invalid data signal isoutput, the on-timing of drive transistor 2 b is determined by the delaytime of delay circuits 131 and 137. Therefore, drive transistor 2 b canbe turned on at an appropriate timing according to the absence/presenceof an invalid data signal.

Similar to the first modification, various changes can be made on theoutput control circuit of FIG. 29.

[Modification 4]

Referring to FIG. 31, an output control circuit 100 includes an invertercircuit 110 and an AND circuit 111 responsive to a rise of the signalpotential on node N2 for generating a one shot pulse signal of an Hlevel, an NAND circuit 141 for receiving output designating signal DOTand an output of AND circuit 111, and a latch circuit 142 for receivinga signal on node N2 and an output of NAND circuit 141. Latch circuit 142includes NAND circuits NA15 and NA16. NAND circuit NA15 has one inputreceiving an output of NAND circuit 141 and the other input receiving anoutput signal of NAND circuit NA16. NAND circuit NA16 has one inputreceiving a signal potential on node N2 and the other input receiving anoutput of NAND circuit N25.

Output control circuit 100 further includes a delay circuit 143 forreceiving an output of NAND circuit NA15 of latch circuit 142, a delaycircuit 146 for receiving a signal on node N2, an AND circuit 144 forreceiving outputs of delay circuits 146 and 143, an inverter 147 forinverting a signal on node N2, and an NOR circuit 145 for receiving anoutput of inverter 147. A drive control signal is provided from NORcircuit 145 to the gate of drive transistor 2 b via node N31.

Delay circuits 143 and 146 delay an applied signal for a predeterminedtime and invert the logic thereof. Inverter circuit 144 also functionsas a delay circuit.

The operation of the output control circuit of FIG. 31 will be describedwith reference to the operation waveform diagrams of FIGS. 32A and 32B.

An operation in the case where an invalid data signal is output will bedescribed hereinafter with reference to FIG. 32A.

First, output permission signal OEM is pulled up to an H level, but thepotential of node N2 is maintained at an L level since internal readoutdata signal ZDD is at an L level.

When output designation signal DOT is pulled down to an L level, a validdata signal of an H level is transmitted on internal readout data line915 b at an elapse of a predetermined time period. According to internalreadout data signal ZDD of an H level, the potential of node N2 ispulled up to an H level. In response to rise of the potential of nodeN2, a one shot signal of an H level is provided from AND circuit 111.The pulse width of the one shot pulse signal from AND circuit 111 isdetermined by the delay time of inverter circuit 110.

When this one shot pulse signal is generated from AND circuit 111,output designating signal DOT still remains at an L level, and theoutput of NAND circuit 141 is fixed to an H level. In latch circuit 142,when node N2 maintains an L level at the initial state, a signal of an Hlevel is provided from NAND circuit NA16, and the signal of an L levelis provided from NAND circuit NA15. Therefore, the signal from NANDcircuit NA16 to node N106 is maintained at the H level even when thepotential of node N2 is driven to an H level. In other words, the latchstate of latch circuit 142 exhibits no change, and the potential of nodeN105 is fixed at an L level.

At an elapse of a delay time of inverter 147 following the rise of thepotential of node N2 to an H level, the signal from inverter circuit 147to node N107 attains an L level. AND circuit 144 receives a signal of anH level from delay circuit 143. Therefore, at an elapse of a delay timeof delay circuit 146 from the rise of the potential of node N2 to an Hlevel, the potential of node N108 is driven to an L level, and theoutput of AND circuit 144 attains an L level. NOR circuit 145 receivessignals of an L level at both inputs, whereby the potential of node N31is increased. As will be described afterwards, NOR circuit 145 and ANDcircuit 144 form a composite gate, in which only one p channel MOStransistor is turned on at the output portion. As a result, thepotential of node N31 rises gently, and the driving capability of drivetransistor 2 b is gradually increased. Therefore, the fall of thepotential of output node 6 is gentle. Even in the case where an invalidsignal is output, the driving capability of drive transistor 2 b isincreased at an elapse of a sufficient time period. Thus, a signal of anL level can be provided stably with no generation of ringing.

An operation in the case where an invalid data is not output will bedescribed hereinafter with reference to FIG. 32B.

First, output designating signal DOT is generated. In response, validdata signal ZDD is pulled up to an H level. In this state, the potentialof node N2 is at an L level yet.

Following the rise (generation) of output designating signal DOT to an Hlevel, output permission signal OEM is pulled up to the H level, and thepotential of node N2 is driven to an H level. In response, AND circuit111 provides a one shot pulse signal of an H level according to thedelay function of inverter circuit 110. In response to the one shotpulse of an H level from AND circuit 111, a one shot pulse signal of anL level is generated from NAND circuit 141 onto node N104 (signal DOTalready attains an H level). In response to a signal of an L level onnode N104, the output of NAND circuit NA15 of latch circuit 142 ispulled up to an H level. According to a signal of an H level provided tonode N105 from NAND circuit NA15, a signal of an L level is providedfrom NAND circuit NA16 to node N106. This state is maintained during theperiod of H level of node N2.

In response to a rise of the potential of node N2, the output ofinverter circuit 147 is pulled down to an L level, whereby the output ofNOR circuit 145 is gradually increased. Then, the output of delaycircuit 146 is pulled down to an L level at an elapse of a delay time inresponse to a rise of the signal on node N2, and the output of ANDcircuit 144 attains an L level. Furthermore, the output of delay circuit143 is pulled down to an L level. In the composite gate formed of ANDcircuit 144 and NOR circuit 145, at least two p channel MOS transistorsare turned on to increase the potential of node N31 by a greater drivingcapability differently from the case where an invalid data signal isoutput. Drive transistor 2 b is turned on at a relatively advancedtiming after a valid data signal appears on node N2. Thus, the potentialof output node 6 is reduced at a high speed.

As described above, output node 6 can be discharged to the level ofground potential at an optimum timing according to a structure where thelogic gate of controlling the potential of drive transistor 2 b isformed of a composite gate, and the number of charging transistors whichare turned on out of the transistors of the composite gate is changedaccording to the absence/presence of an invalid data output.

FIG. 33 shows a specific structure of the composite gate of the ANDcircuit and NOR gate of FIG. 31. Referring to FIG. 33, NAND circuit 144and NOR circuit 145 include p channel MOS transistors 151 and 152connected in series between a power potential supply node and node N31,and having the gates connected to nodes N107 and N102, p channel MOStransistors 153 and 154 connected in series between the supply node ofpower supply potential and node N31, and having their gates connected tonodes N107 and N108, respectively, an n channel MOS transistor 155connected between output node N31 and the ground potential node, andhaving its gate connected to node N107, and n channel MOS transistors156 and 157 connected in series between node N31 and the groundpotential node for receiving the potentials of nodes N108 and N109 attheir respective gates.

According to the composite gate structure of FIG. 33, NOR circuit 145functions as an inverter circuit when the potential of node N107 attainsan L level. When the potential of node N107 attains an L level,transistors 151 and 153 are turned on and transistor 155 is turned off.When the potential of node N108 attains an L level, transistor 154 isturned on. Therefore, when there is a possibility of an invalid datasignal output, output node N31 is charged only via transistors 153 and154. In this operation, transistor 156 is turned off, so that adischarging path does not exist, and the potential of node N31 risesgently.

When the potentials of nodes 108 and N109 attain an L level, thepotential of node N107 already attains an L level. Therefore, node N31is charged via transistors 151 and 152, and further by transistors 153and 154, while all the discharging transistors 155, 156 and 157 areturned off. Therefore, node N31 is charged at a relative high speed, andthe potential is pulled up speedily.

When the potential of node N107 is pulled up to an H level, transistor155 is turned on, and node N31 is discharged via transistor 155 toattain an L level. In this operation, transistors 151 and 153 are off.

By using the composite gate as shown in FIG. 33, the gate of drivetransistor 2 b, i.e. the rising speed of the potential of node N31 canbe switched according to absence/presence of an output of an invaliddata signal. Therefore, the driving capability of drive transistor 2 bcan be increased at an optimum timing.

In the structure of the composite gate of FIG. 33, p channel MOStransistors 151 and 153 may be combined together into one p channel MOStransistor. Similar to the previous embodiments, various modificationscan be applied to the output control circuit of FIG. 31.

[Modification 5]

Referring to FIG. 34 showing an output circuit of a fifth modificationof the fourth embodiment, an output circuit includes a delay circuit 161for delaying output permission signal OEM for a predetermined time T5,an inverter circuit 5 for inverting internal readout data ZDD, an ANDcircuit 3 for receiving outputs of delay circuit 161 and invertercircuit 5, an AND circuit 4 for receiving output permission signal OEMand internal readout data signal ZDD, a drive transistor 1 formed of ann channel MOS transistor and rendered conductive in response to anoutput of AND circuit 3 for charging output node 6 to the level of powersupply potential Vcc, and a drive transistor 2 a of an n channel MOStransistor and rendered conductive in response to an output of ANDcircuit 4 for discharging output node 6 to the level of groundpotential.

The output circuit further includes a delay circuit 160 for delaying anoutput of AND circuit 4 for a predetermined time T6, and an AND circuit90 for receiving a signal of node N2 (output of AND circuit 4) and anoutput of delay circuit 160. The output of AND circuit 90 is applied tothe gate of drive transistor 2 b. The current driving capability ofdrive transistor 2 b is set greater than that of drive transistor 2 a.The operation of the output circuit of FIG. 34 will be described withreference to the operation waveform diagrams of FIGS. 35A and 35B.

An operation in a case where an invalid data signal is not output willbe described with reference to FIG. 35A. In the case where an invaliddata signal is not output, output permission signal OEM is pulled up toan H level after the rise of internal readout data signal ZDD to an Hlevel. In response to a rise of output permission signal OEM, ANDcircuit 4 provides a signal of an H level to node N2. In response to arise of the potential of node N2, drive transistor 2 a is turned on,whereby the potential of output node 6 is discharged gently towards thelevel of the ground potential.

At an elapse of a predetermined time period T6 of delay circuit 160, theoutput of delay circuit 160 attains an H level, and the output of ANDcircuit 90 attains an H level. As a result, drive transistor 2 b isturned on, whereby the potential of output node 6 is discharged to thelevel of ground potential at high speed. The potential of output node 6is low enough when drive transistor 2 b is turned on, so that an outputsignal can be provided stably with no ringing even when the potential ofoutput node is discharged at high speed.

Node N1 maintains the potential of an L level since internal readoutdata signal ZDD already attains an H level when output permission signalOEM is pulled up to an H level. Therefore, drive transistor 1 is keptturned off.

An operation in the case where an invalid data signal is output will bedescribed with reference to FIG. 35B. When an invalid data signal isoutput, output permission signal OEM is pulled up to an H level, whileinternal readout data signal ZDD still maintains an L level. The outputof inverter circuit 5 is at an H level. At an elapse of a delay time ofT5 of delay circuit 161 from the rise of output permission signal OEM toan H level, the output of AND circuit 3 (potential of node N1) is pulledup to an H level, whereby drive transistor 1 is turned on to chargeoutput node 6.

Then, when a valid data signal is transmitted and internal readout datasignal ZDD is pulled up to an H level, the output of inverter circuit 5is pulled down to an L level. As a result, the output of AND circuit 3(potential of node N1) is driven to an L level, and drive transistor 1is turned off. In response to the transition of internal readout datasignal ZDD to an H level, the output of AND circuit 4 (potential of nodeN2) is pulled up to an H level, and drive transistor 2 a is turned on.As a result, the potential of output node 6 is discharged gently to thelevel of ground potential.

At the elapse of a delay time T6 of delay circuit 160, delay circuit 160is pulled up to an H level, and the output of AND circuit 90 is drivento an H level. As a result, drive transistor 2 b is turned on, and thepotential of output node 6 is discharged to the level of groundpotential at a high speed.

In the case where this invalid data signal is output, the period duringwhich the invalid data signal appears on output node 6 is reduced bydelay time T5 of delay circuit 161. Therefore, the time duration of aninvalid data signal appearing on output node 6 is shortened, so that theamount of a potential change due to the invalid data signal of outputnode 6 can be reduced. As a result, when drive transistor 2 b is turnedon following the turn on of drive transistor 2 a to discharge potentialoutput node 6, the potential of output node is sufficiently low that anoutput signal can be provided stably with generation of ringingeffectively prevented.

The output of an invalid data signal can be prevented by setting thedelay time T5 of delay circuit 161 such that a signal of an H level isnot provided from AND circuit 3 to node N1 until internal readout datasignal ZDD attains a valid state of an H level.

In the case where an invalid data signal is not output (refer to FIG.35A) according to the structure of FIG. 34, the time required for thepotential of node N1 to be driven to an H level from the rise of outputpermission signal OEM to an H level is delayed by delay time T5 of delaycircuit 161. Therefore, in this case, only the access time of an Houtput is delayed. When the access time is determined by an output of anL level, and the H access time period is shorter than an L access time,degradation of the access time can be prevented.

FIG. 34 shows a structure of discharging output node 6 to the level ofground potential. In the structure shown in FIG. 34, generation ofringing at the rise of the potential of output node 6 can be preventedby providing a structure similar to that of delay circuit 161 for ANDcircuit 4, and by providing delay circuit 160 and AND circuit 90 to nodeN1, and providing a drive transistor having a driving capability greaterthan that of drive transistor 1 in parallel thereto.

Delay circuits 161 and 160 shown in FIG. 34 may have the number ofstages of inverters set to an appropriate value. Furthermore, delaycircuits 160 and 161 may be realized by a delay element different froman inverter.

[Modification 6]

Referring to FIG. 36 showing a structure of an output circuit of a sixthmodification, the output circuit includes an inverter circuit 5 forinverting internal readout data signal ZDD, an AND circuit 3 forreceiving output permission signal OEM and an output of inverter circuit5, an AND circuit 4 for receiving output permission signal OEM andinternal readout data signal ZDD, a delay circuit 160 a for delayingoutput permission signal OEM for a predetermined time Ta, and a delaycircuit 160 b for delaying an output of AND circuit 4 for apredetermined time period of Tb. Delay time Ta of delay circuit 160 a isset shorter than delay time Tb of delay circuit 160 b. Delay time Ta ofdelay circuit 160 a is set to such a time width that an invalid datasignal is prevented from appearing on node N2 in reading out a datasignal of an L level. Delay time Ta of delay circuit 160 a is set to amaximum value, for example, of a specification value of the timerequired from a change of a column address signal to a fall of columnaddress strobe signal ZCAS to an L level. Therefore, transmission of aninvalid data signal to node N2 can be prevented. The operation of thecircuit of FIG. 36 will be described with reference to the operationwaveform diagram of FIG. 37 for the case where a data output signal Q ofan H level is provided.

In this case, internal readout data signal ZDD attains an L level(internal readout data signal ZDD is precharged to an L level duringstandby or prior to a data readout operation). Under this state, whenoutput permission signal OEM rises to an H level, AND gate 3 provides asignal of an H level on node N1. In response to a rise of the potentialof node N1, drive transistor 1 a is turned on. The current drivingcapability of drive transistor 1 a is set to a relatively low level. Asa result, output node 6 is discharged gently via drive transistor 1 a.

At an elapse of a delay time Ta of delay circuit 160 a, the output ofdelay circuit 160 a is pulled up to an H level, and the output of ANDcircuit 90 a is driven to an H level. As a result, drive transistor 1 ais turned on. Drive transistor 1 b has its current driving capabilityset to a sufficient high level. Therefore, output node 6 is charged athigh speed by drive transistor 1 b, so that the potential thereof risesspeedily.

An operation in the case where an invalid data signal is output duringan L data output will be described with reference to FIG. 38. First,output permission signal OEM is pulled up to an H level, while internalreadout data signal ZDD is at an L level and the output of invertercircuit 5 is at an H level. In response to a rise of output permissionsignal OEM, AND circuit 3 provides a signal of an H level to node N1. Inresponse to a rise of the signal potential on node N1, drive transistor1 a of a low current driving capability is turned on, whereby thepotential of output node 6 is gently increased.

Then, a valid data signal is transmitted, and internal readout datasignal ZDD is pulled up to an H level. AND circuit 3 provides an outputof an L level, whereby drive transistor 1 a is turned off. In responseto internal readout data signal ZDD of an H level, AND circuit 4provides a signal of an H level to node N2, whereby drive transistor 2 aof a low current driving capability is turned on. As a result, theincreased potential of output node 6 is gently discharged towards thelevel of the ground potential.

At an elapse of a delay time Tb of delay circuit 160 b, the output ofdelay circuit 160 b attains an H level (potential of node N30 b), andAND circuit 90 b provides a signal of an H level to node N31 b. As aresult, drive transistor 2 b of a great current driving capability isturned on, whereby output node 6 is discharged to the level of groundpotential at high speed.

Even in the case where an invalid data signal is output, drivetransistor 1 a of a low current driving capability is first turned on tocharge output node 6. The potential increase of output node 6 is smallsince the current driving capability of drive transistor 1 a is low.Therefore, the potential of output node 6 can be set to a sufficient lowlevel to effectively prevent generation of ringing.

Drive transistor 1 b of a great current driving capability maintains anoff state since the potential level of node N31 a is fixed to an Llevel. This is because the potential of node N1 already attains an Llevel at the transition of the output delay circuit 160 a to an H level.

The operation in the case where an invalid data signal is not outputwill be described with reference to FIG. 39, wherein internal readoutdata signal ZDD rises to an H level, and therefore the potential of nodeN1 is fixed to an L level.

When output permission signal OEM rises to an H level, the potential ofnode N2 is pulled up to an H level via AND circuit 4. At an elapse of apredetermined time Ta, the output of delay circuit 160 a is pulled up toan H level. However, since the potential of node N1 attains an L level,the output of AND circuit 90 a is pulled down to an L level, and drivetransistors 1 b and 1 a maintain an OFF state.

In response to a rise of the potential of node N2, drive transistor 2 ais turned on, whereby output node 6 is discharged gently. Then, when theoutput of delay circuit 160 b is pulled up to an H level, the potentialof node N31 b is driven to an H level via AND circuit 90 b, wherebydrive transistor 2 b is turned on. As a result, output node 6 isdischarged to the level of ground potential at high speed. When drivetransistor 2 b is turned on, the potential of output node 6 is alreadyset to a sufficiently low level by drive transistor 2 a. Therefore, anoutput signal can be generated stably with no generation of ringing.

In the structure shown in FIG. 36, the difference in the current drivingcapability of drive transistors 1 a and 1 b can be realized by selectingthe size or the gate width, or the ratio of the gate width to the gatelength of these transistors appropriately. Furthermore, a structure maybe employed in which a voltage of the level of power supply voltage Vccis applied to the gate of drive transistor 1 a, and a boosted powersupply voltage is applied to the gate of drive transistor 1 b. Theadjustment of the gate voltage of drive transistors 1 a and 1 b can becombined with the adjustment of the size. The structure ofdifferentiating the gate voltages may be applied to drive transistors 2a and 2 b discharging output node 6 to the level of the groundpotential.

Similar to the prior modification 5, a structure may be employed inwhich output permission signal OEM is applied to AND circuit 3 via adelay circuit as in the output circuit of FIG. 36. In this case, therising time of the potential of node N can be delayed, and the timeperiod of an invalid data signal output can be reduced.

Therefore, the potential amplitude of output node 6 can further bereduced.

By providing a circuit configuration similar to that shown in FIG. 36for a drive transistor increasing the potential of output node 6,increase in the potential amplitude of output node 6 can be preventedwhen an invalid data signal attains an L level and a valid data signalattains an H level.

[Modification 7]

Referring to FIG. 40 showing a structure of an output circuit of aseventh modification, an output circuit includes an inverter circuit 5for inverting readout internal data signal ZDD, an AND circuit 4 forreceiving output designating signal DOT, output permission signal OEMand an output of inverter circuit 5, a drive transistor 1 renderedconductive in response to an output of AND circuit 3 for charging outputnode 6 to the level of power supply potential Vcc, an AND circuit 4 forreceiving output permission signal OEM and internal readout data signalZDD, and a drive transistor 2 a of a relatively low current drivingcapability and rendered conductive in response to an output of ANDcircuit 4 for discharging output node 6 to the level of groundpotential.

The output circuit further includes a delay circuit 160 for delaying anoutput of AND circuit 4 (potential of node N2) for a predetermined timeperiod, and an AND circuit 90 for receiving an output of delay circuit160 and a signal of node N2. The output of AND circuit 90 is provided tothe gate of drive transistor 2 b of a great current driving capability.The operation of the output circuit of FIG. 40 will be described withreference to the operation waveform diagram of FIG. 41.

First, an operation in the case where an invalid output data signalattains an H level, and a valid data signal attains an L level will bedescribed. In this case, prior to a fall of output designating signalDOT, output permission signal OEM is pulled up to an H level. Internalreadout data signal ZDD on internal data bus line 915 b attains an Llevel, and the output of inverter circuit 5 attains an H level.Therefore, in response to a rise of output permission signal OEM, ANDcircuit 3 provides a signal of an H level on node N1. In response to arise of the potential on node N1, drive transistor 1 is turned on. Theoutput of AND circuit 4 (potential of node N2) is at an L level, anddrive transistors 2 a and 2 b are turned off. Therefore, output node 6is charged via drive transistor 1 to have the potential thereofincreased.

The fall of output designating signal DOT causes the potential of node Nto be pulled down to an L level, whereby drive transistor 1 is turnedoff. Then, in response to a fall of output designating signal DOT, avalid data signal ZDD of an H level is transmitted on internal data busline 915 b, and a signal of an L level is provided from inverter circuit5 to node N90. As a result, the output of AND circuit 3 currentlyproviding data ZDD, i.e. the potential of node N1, is fixed at an Llevel.

When internal readout data signal ZDD attains an H level, AND circuit 4provides a signal of an H signal on node N2, whereby drive transistor 2a is turned on. As a result, output node 6 is discharged gently, so thatthe potential thereof is gradually reduced.

At an elapse of a predetermined time, the output of delay 150 attains anH level, and a signal of an H level is provided by AND circuit 90 ontonode N31. As a result, drive transistor 2 b is turned on, whereby thepotential of output node 6 is discharged to the level of groundpotential at high speed.

According to the structure shown in FIG. 40, the ON time period of drivetransistor 1 for discharging output node 6 is extremely short even whenan invalid data signal is output. Therefore, the potential amplitude ofoutput node 6 can be made small. Furthermore, output of invalid data canbe completely prevented in the case where output permission signal OEMattains an H level following an L period of output designating signalDOT. When an invalid data signal of an H level is output, internalreadout data signal ZDD is fixed at an L level as shown by the brokenline in FIG. 41. In this case, the output of inverter circuit 5 is at anH level, and the potential of node N1 is driven to an H level inresponse to a rise of output designating signal DOT to an H level. Incontrast, the output of AND circuit 4 maintains an L level, and drivetransistors 2 a and 2 b maintain an off state. Therefore, output node 6is charged to the level of power supply potential Vcc via drivetransistor 1. In other words, when a valid output data signal attains anH level, drive transistor 1 is turned on in response to a rise of outputpermission signal OEM, and then turned off in response to a transitionof output designating signal DOT to an L level. Then, when outputdesignating signal DOT attains an H level again, drive transistor 1 isturned on again.

An operation in the case where an invalid data signal is not output inreading out an L output data will be described with reference to FIG.42. Output designating signal DOT first falls to an L level. Under thisstate, internal readout data signal ZDD is at an L level, and the outputof inverter circuit 5 (potential of node N90) is at an H level. Thepotential of node N1 is at an L level since output permission signal OEMis at an L level.

At an elapse of a predetermined time period from the fall of outputdesignating signal DOT to an L level, a valid data signal is transmittedto internal data bus line 915 b, whereby internal readout data signalZDD is pulled up to an H level. As a result, the potential of node N90is pulled down to an L level, and the potential of node N1 is fixed toan L level during the reading out time period of internal readout datasignal ZDD. The potential of node N2 is still at an L level since outputpermission signal OEM is at an L level. In response to output permissionsignal OEM pulled up to an H level, the potential of node N2 is pulledup to an H level via AND circuit 4. As a result, drive transistor 2 a isturned on, whereby output node 6 is driven to the level of groundpotential gently. Then, at an elapse of a predetermined time period, theoutput of delay circuit 160 attains an H level, and the output of ANDcircuit 90 attains an H level. Responsively, drive transistor 2 b isturned on, whereby output node 6 is discharged to the level of groundpotential at high speed. The potential of output node 6 is alreadyreduced to a sufficient low level when drive transistor 2 b is turned,so that an output signal can be output stably with no generation ofringing.

In the structure of FIG. 40, a one shot pulse signal generated inresponse to column address transition detection signal φATD andattaining an L level at a timing earlier than that of output designatingsignal DOT may be used instead of output designating signal DOT. Thiscan be realized by employing an appropriate delay circuit in one shotpulse generation circuit 50 of FIG. 5. By using such a signal, the pulsewidth of a one shot pulse signal generated in response to the rise ofoutput permission signal OEM can further be reduced according to theoperation waveform diagram of FIG. 41. Furthermore, the output timeperiod of an invalid data signal output of an H level can be reduced.Also, the potential amplitude of output node 6 can further be reduced.

By providing a signal falling to an L level from an H level at a timingearlier than the transition of output permission signal OEM to an Hlevel from an L level to AND circuit 3 in response to column addresstransition detection signal φATD, generation of an invalid data signalat node N1 can be prevented. This is implemented by using a circuit inwhich a one shot pulse signal of an L level of a predetermined timewidth is generated in response to a fall of the potential of output nodeN14 of a latch circuit in the structure of FIG. 5. Such a signalgeneration circuit may employ an AND circuit receiving a signal on nodeN14 and output designating signal DOT. By using such a structure, theoutput of an invalid data signal onto node N1 can be prevented.

In FIG. 40, a structure may be employed in which output permissionsignal OEM is applied to AND circuit 3 via a delay circuit. In thiscase, the potential amplitude of output node 6 can be reduced byreducing the time period of an invalid data signal output at node N1. Bysetting an appropriate delay time of this delay circuit, generation ofan invalid data signal in node N1 can be reliably prevented.

[Modification 8]

FIG. 43 shows an eighth modification of the output circuit. Referring toFIG. 43, three drive transistors 2 a, 2 b and 2 c are parallely providedfor discharging output node 6. Drive transistors 2 a, 2 b and 2 c havegate widths W made sequentially greater in this order. In other words,the current driving capabilities of drive transistors 2 a, 2 b and 2 care differentiated from each other. An output of AND circuit 90 a isprovided to the gate of drive transistor 2 b. AND circuit 90 a receivesthe potential on node N2 and an output of delay circuit 160 a.

Delay circuit 160 a delays the potential signal of node N2 for apredetermined time period. The output of delay circuit 160 a is furtherdelayed by delay circuit 160 b. An output of AND circuit 90 b isprovided to the gate of drive transistor 2 c. AND circuit 90 b receivesa signal on node N2 and an output of delay circuit 160 b.

According to the structure of the output circuit of FIG. 43, the driveof the potential of node N2 to an H level causes drive transistor 2 a tobe turned on, whereby output node 6 is discharged gently. At an elapseof a predetermined time period, the output of AND circuit 90 a attainsan H level, whereby drive transistor 2 b is turned on. As a result,output node 6 is discharged to the level of ground potential.

At a further elapse of a predetermined time period, the output of delaycircuit 160 b is pulled up to an H level. In response to an output ofAND circuit 90 b, drive transistor 2 c is turned on, whereby output node6 is discharged to the level of ground potential at high speed. Byproviding three drive transistors for discharging output node 6 whichare turned on at different timings, an output signal can be generatedstably with no generation of ringing. The structure of the outputcircuit of FIG. 43 can be utilized in combination with any of the firstto third embodiments.

[Modification 9]

FIG. 44 shows a ninth modification of the fourth embodiment. Referringto FIG. 44, a structure of a gate circuit 90 is shown for directlydriving drive transistor 2 b for discharging output node 6 to the levelof ground potential. Gate circuit 90 can be used in various embodimentsand modifications. FIG. 44 shows a basic circuit configuration as anoutput circuit.

In FIG. 44, drive transistor 2 a is driven by NAND circuit 4 a andinverter circuit 4 b. NAND circuit 4 a receives output permission signalOEM and internal readout data signal ZDD. Inverter circuit 4 b receivesan output of NAND circuit 4 a for transmitting a signal of a logiccorresponding to internal readout data signal ZDD onto node N2.

The output circuit further includes a delay circuit 171 a for delayingan output of NAND circuit 4 a for a predetermined time period, a delaycircuit 171 b for delaying an output of delay circuit 171 a, and a gatecircuit 90 for driving drive transistor 2 b according to an output ofNAND circuit 4 a and outputs of delay circuits 171 a and 171 b. Gatecircuit 90 corresponds to AND circuits 90 a and 90 b of FIG. 43.

Gate circuit 90 includes p channel MOS transistors 172, 173 and 174connected in parallel between a power supply potential node and internalnode 177. Outputs of NAND circuit 4 a, delay circuit 171 a, and delaycircuit 171 b are provided to the gates of transistors 172, 173 and 174,respectively.

Gate circuit 90 further includes an inverter circuit provided betweeninternal node 177 and a ground potential. This inverter circuit includesa p channel MOS transistor 175 provided between output node N31 andinternal node 177, and receiving an output of NAND circuit 4 a at itsgate, and an n channel MOS transistor 176 provided between output nodeN31 and the ground potential node and receiving an output of NANDcircuit 4 a at its gate. The operation of gate circuit 90 will now bedescribed.

When the potential of node N2 attains an L level, NAND circuit 4 aprovides a signal of an H level. Under this state, all transistors172-175 attain an off state, and transistor 176 is ON. Therefore, outputnode N31 attains an L level.

When the output of NAND circuit 4 a attains an L level, the potential ofnode N2 attains an H level, whereby drive transistor 2 a is turned on.Therefore, output node 6 is discharged gently by drive transistor 2 a.Under this state, a fall of the output of NAND circuit 4 a to an L levelturns on transistors 172 and 175, and turns off transistor 176 b.Therefore, output node N31 is charged gently via transistors 172 and175, to have the potential risen gently. As a result, the drivingcapability of drive transistor 2 b increases slightly.

Then, when the output of delay circuit 171 a attains an L level,transistor 173 is turned on, and node N31 is charged via transistors172, 173 and 175 to have the potential thereof increased slightly. Thedriving capability of drive transistor 2 b is further slightlyincreased.

At an elapse of a predetermined time period, the output of delay circuit171 b attains an L level, and transistor 174 is turned on. As a result,current flows to transistor 175 via transistors 172-174, whereby thepotential of node N31 is driven at a high speed. The current drivingcapability of drive transistor 2 b is increased rapidly.

An effect similar to that of the previous embodiments and modificationscan be obtained without using a delay circuit by differentiating therising speed of the output potential of gate circuit 90 over a timeperiod to vary the current driving capability of drive transistor 2 bover the time period. As shown in FIG. 44, the current changing ratewith respect to time that generates ringing at output node 6, i.e. di/dtcan be reduced even when the current driving capability of drivetransistor 2 b is increased over time. Therefore, generation of ringingcan be reliably prevented.

Embodiment 5

In a semiconductor device, an upper limit value Vcmx and a lower limitvalue Vcmn are set for power supply voltage Vcc in order to guarantee astable operation. In the case of an operating power supply voltage Vccof 5 V, for example, the upper limit value Vcmx is set to 5.5 V, and thelower limit value Vcmn is set to 4.5 V in the specification. A variationof power supply voltage Vcc in the range of ±10% of the rated value ofpower supply voltage Vcc is allowed.

Similarly, an upper limit value Tamx and a lower limit value Tamn areset with respect to operating temperature Ta. The range of 0 to 70° C.is defined in the specification as a range of operating temperature Ta.

In a circuit with MOS transistors as the components, the operating speedis increased as power supply voltage Vcc is increased. The currentdriving capability of a MOS transistor is determined by the gate voltage(gate-source voltage difference). This is because the gate-sourcepotential difference is determined by power supply voltage Vcc.

In a circuit with MOS transistors as the components, the operating speedis also increased as the operating temperature Ta is lowered. This issince a higher operating temperature causes a greater resistance in thediffusion region and the threshold voltage is increased due to influenceof hot electrons, so that a current driving capability is reduced.

A typical example demonstrating such circuit characteristics can befound in a phenomenon that access time ta becomes shorter in proportionto power supply voltage Vcc and becomes longer in proportion to anoperating temperature in a semiconductor memory device.

A structure reliably preventing generation of ringing independent ofvariation in power supply voltage Vcc and operating temperature Ta willbe described.

FIGS. 45A and 45B show the characteristics of a first control voltageused in the present fifth embodiment. A first control voltage VNincreases in proportion to an ambient temperature T as shown in FIG.45A. In other words, first control voltage VN has a positive temperaturecoefficient. Furthermore, first control voltage VN is reduced inproportion to a power supply voltage Vcc as shown in FIG. 45B. In otherwords, first control voltage VN has a negative dependency on powersupply voltage Vcc.

FIGS. 46A and 46B show the temperature and power supply voltagedependency characteristics of a second control voltage used in thepresent fifth embodiment. As shown in FIG. 46A, second control voltageVP is lowered in proportion to an ambient temperature T. In other words,second control voltage VP has a negative temperature coefficient.Furthermore, as shown in FIG. 46B, second control voltage VP increasesin proportion to a power supply voltage Vcc. In other words, secondcontrol voltage VP has a positive dependency on power supply voltageVcc. The delay time of a delay stage is adjusted using first and secondcontrol voltages VN and VP having opposing temperature and power supplyvoltage dependency characteristics.

FIG. 47A shows a first structure of an inverter circuit forming a delaystage used in the present fifth embodiment. Referring to FIG. 47A, aninverter circuit forming a delay stage includes p channel MOStransistors 201 and 202 connected in series between a supply node ofpower supply voltage Vcc and output node 205, and an n channel MOStransistor 203 provided between output node 205 and the ground potentialnode. Second control voltage VP is applied to the gate of p channel MOStransistor 201. MOS transistors 202 and 203 both have their gatesconnected to input node 204. The operation characteristics of theinverter circuit of FIG. 47A will be described with reference to FIG.47B.

When power supply voltage Vcc approaches the lower limit value Vcmn orwhen operating temperature T approaches the upper limit temperatureTamx, second control voltage VP is reduced. Therefore, the currentdriving capability of p channel MOS transistor 201 is made greater thanthe case under the condition of upper limit value Vcmx of power supplyvoltage Vcc and lower limit value Tamn of operating temperature T.

When an input signal IN applied to input node 204 attains a low level,MOS transistor 202 is turned on, and MOS transistor 203 is turned off.Output node 205 is charged to the level of power supply voltage Vcc viatransistors 201 and 202. Second control voltage VP is set to a valuesufficiently lower than power supply voltage Vcc, so that transistor 201can pass through power supply voltage Vcc. An optimum value of secondcontrol voltage VP is determined according to the actual operatingcharacteristics of the device.

When power supply voltage Vcc is near the lower limit value Vcmn oroperating temperature T is near the upper limit value Tamx, output node205 is pulled up to a high level at a high speed (shown in a broken linein FIG. 47B).

When input signal IN attains a high level, MOS transistor 203 is turnedon, whereby output node 205 is discharged to the level of the groundpotential. The discharging rate of output node 205 is determined by thecurrent driving capability of transistor 203. More specifically, when adelay stage is formed using an inverter circuit shown in FIG. 47A, thetime required for transmitting a signal of a low level becomes longerwith power supply voltage Vcc at the upper limit value and ambienttemperature T at the lower value.

Another structure and operation characteristics thereof of an invertercircuit forming a delay stage will be described with reference to FIGS.48A and 48B. Referring to FIG. 48A, an inverter circuit 210 includes a pchannel MOS transistor 211 provided between a power supply potentialnode and output node 215, and n channel MOS transistors 212 and 213provided in series between output node 215 and a ground potential node.Input signal IN is applied via input node 214 to the gates of MOStransistors 211 and 212. First control voltage VN is applied to the gateof MOS transistor 213. The operation characteristics of the invertercircuit shown in FIG. 48A will be described with reference to FIG. 48B.

First control voltage VN has a negative dependency on power supplypotential Vcc and a positive temperature coefficient. When input signalIN attains a high level, MOS transistor 212 is turned on. When powersupply potential Vcc is near an upper limit value Vmx or ambienttemperature T is near a lower limit value Tamn, first control voltage VNis reduced. Therefore, in this state, the current driving capability ofMOS transistor 213 is made low. First control voltage VN is set to avalue sufficiently higher than the threshold voltage of MOS transistor213. Therefore, output node 215 is discharged in a more gentle mannerwhen power supply voltage Vcc takes a high value or when ambienttemperature T takes a low value than the otherwise case. Morespecifically, when a signal of a high level is transmitted to a delaystage formed of an inverter circuit shown in FIG. 48A, the propagationtime is increased when power supply potential Vcc takes a value close toupper limit value Vmx or when ambient temperature T takes a value closeto lower limit value Tamn in comparison with the opposite case.

FIGS. 49A and 49B show a structure and the operating characteristics ofan inverter circuit forming a delay stage according to another structurein the present fifth embodiment. Referring to FIG. 49A, an invertercircuit 220 includes p channel MOS transistors 221 and 222 connected inseries between output node 226 and the power supply potential node, andn channel MOS transistors 223 and 224 connected in series between outputnode 226 and the ground potential node. MOS transistors 222 and 223 havetheir gates connected together to input node 225 to receive an inputsignal IN. Second control voltage VP is applied to the gate of MOStransistor 221. First control voltage VN is applied to the gate of MOStransistor 224. The operation of the inverter circuit of FIG. 49 will bedescribed with reference to FIG. 49B.

Inverter circuit 220 of FIG. 49A has a structure of a combination ofinverter circuits 200 and 210 shown in FIGS. 47A and 48A. Therefore,when a signal of a high level is applied to input node 225, output node226 is discharged at a speed higher than that when power supplypotential Vcc is low or when ambient temperature T is high in comparisonwith the opposite case. Therefore, when a delay stage is formed using aninverter circuit shown in FIG. 49A, the propagation delay time withrespect to a signal of a high or low level is increased when powersupply voltage Vcc approximates the upper limit value or when ambienttemperature T approximates the lower limit value.

By forming a delay stage using the above-described inverter circuit, anoutput circuit Q can be generated stably with no variation in the accesstime and with no ringing independent of variation in power supplyvoltage Vcc and ambient temperature T.

FIG. 50A shows an application of the delay stage of the fifthembodiment. In FIG. 50A, a delay stage is additionally provided thecircuit for generating output permission signal OEM shown in FIG. 5.Delay stage 230 includes cascaded inverters 231, 232, 233 of threestages for delaying and inverting a delayed signal ZCASE of an internalcolumn address strobe signal. The output of delay stage 230 is providedto flipflop 56. When the output of delay stage 230 attains a high level,output permission signal OEM from inverter circuit 58 is pulled up to ahigh level. Delay stage 230 corresponds to inverter circuit 54 shown inFIG. 5. Delay stage 230 includes three cascaded inverter circuits 231,232, and 233. As inverter circuits 231-233 in delay stage 230, invertercircuit 220 shown in FIG. 49A or inverter circuits 200 and 210 shown inFIGS. 47A and 48A are connected alternately. Generation of outputpermission signal OEM is triggered by a fall of signal ZCASE. Therefore,inverter circuits 200, 210 and 200 are provided in sequence as invertercircuits 231, 232 and 233 included in delay stage 230. When invertercircuit 220 shown in FIG. 49A is to be used, inverter circuits 231-233are all formed of inverter circuit 220.

The operation of the circuit shown in FIG. 50A will be described withreference to FIG. 50B.

In response to output designating signal DOT attaining a low level, avalid data ZDD is provided. A case is considered where output permissionsignal OEM is pulled up to a high level prior to a fall of outputdesignating signal DOT. This state corresponds to the state where aninvalid data signal is output. When power supply voltage Vcc takes avalue close to lower limit value Vcmn or ambient temperature T takes ahigh value in delay stage 230, the delay time thereof is reduced.Therefore, output permission signal OEM is brought up to a high levelmore speedily than the case where power supply voltage Vcc takes a valuenear the upper limit value Vcmx or ambient temperature T takes a valuenear lower limit value Tamn. Therefore, when power supply voltage Vcc ishigh or when ambient temperature T is low, the time period of an invaliddata signal provided from the output node is “reduced”. When powersupply voltage Vcc takes a value near upper limit value Vmx or ambienttemperature T takes a value near lower limit value Tamn, the drivingcapability of the MOS transistor is increased. Therefore, the swingwidth of a voltage at the output node can be reduced to a sufficientlevel by “delaying” the ON time of the MOS transistor driving the outputnode when the current driving capability of the MOS transistor is greatat the time of output of this invalid data signal. Thus, generation ofringing can be reliably prevented.

Similarly, generation of ringing can be prevented to provide an outputdata signal stably even in the case where valid data ZDD is variedfollowing the drive of output permission signal OEM to an H level afteroutput designating signal DOT attains an L level.

When power supply voltage Vcc takes a value near the lower limit value Vcm or ambient temperature T takes a high temperature, the ON timing ofthe MOS transistor driving the output node is “advanced”. However, sincethe current driving capability of the MOS transistor driving the outputnode is low, the swing width of the voltage at the output node is not sogreat, so that generation of ringing can be reliably prevented.Furthermore, when an invalid data signal is not output and a valid datasignal is output (when signal OEM is pulled up to an H level after thetransition of signal DOT to a high level), increase in the access timecan be reliably prevented since the on timing of the MOS transistordriving the output node is “advanced” when the driving capabilitythereof is low. Since the delay time is adjusted according to theoperating conditions, the charging/discharging rate of the output nodecan be set to a constant level independent of the operating conditions.

FIG. 51A shows another application of the delay stage according to thefifth embodiment of the present invention. As shown in FIG. 51A,inverter circuits 241 and 242 of the fifth embodiment of the presentinvention are provided for delay circuit 161 in the output drivingcircuit of FIG. 34. The remaining structure is similar to that shown inFIG. 34. Inverter circuits 241 and 242 utilize inverter circuit 240shown in FIG. 49A or inverter circuits 200 and 210 shown in FIGS. 47Aand 48A. In order to delay the rise of output permission signal OEM to ahigh level, inverter circuit 210 shown in FIG. 48A is used as invertercircuit 241 of the first stage, and inverter circuit 200 of FIG. 47A isused as inverter circuit 242 of the next stage. The operation of theoutput circuit in FIG. 51A will be described with reference to FIG. 51B.

The operation mode of valid data signal ZDD rising to an H levelfollowing the transition of output permission signal OEM to an H levelis considered. This is a mode where an invalid data signal is output. Inresponse to a rise of output permission signal OEM to an H level, theoutput of delay circuit 161 is pulled up, which in turn drives thepotential of node 243 to a high level. The delay time of delay circuit161 is reduced when power supply voltage Vcc takes a value near lowerlimit value Vcmn or when ambient temperature T takes a value near upperlimit value Tamx. Therefore, the potential of node 243 is increasedspeedily when the driving capability of MOS transistor 2 is reduced.Since the current driving capability of MOS transistor 1 is set to a lowvalue, output node 6 is increased gently according to an invalid datasignal. Then, a valid data signal is transmitted, and internal readoutdata signal ZDD is pulled up to an H level to turn off MOS transistor 1.Although the time period TB of the output of this invalid data signal isappreciable, the increase of the potential amplitude of output node 6 isrelatively low since the operating condition is such that the currentdriving capability of MOS transistor 1 is made low. Therefore, even whendrive transistor 2 is turned on, an output data signal can be generatedstably with no ringing.

In contrast, in the case of an operating condition where the currentdriving capability of each of MOS transistors 1 and 2 is increased, thedelay time of delay circuit 161 is increased. More specifically, thedelay time of delay circuit 161 is increased when power supply voltageVcc takes a value approximate to upper limit value Vcmx or ambienttemperature T takes a value approximate to lower limit value Tamx, sothat MOS transistor 1 is turned on at a later timing. Therefore, evenwhen the current driving capability of MOS transistor 1 is great, thetime period of an on state thereof is short, so that the potentialincrease of output node 6 is small. Therefore, even when MOS transistor2 is turned on in response to a transmission of a subsequent valid datasignal, the potential of output node 6 is sufficiently low, so thatgeneration of ringing can be prevented reliably.

When a valid data signal is output, the potential of node 243 is alwaysat the low level, and MOS transistor 1 maintains the off state.

As described above, the potential amplitude of output node 6 can be setsmall regardless of the operating condition. Degradation in the accesstime can be prevented reliably regardless of the operating condition,with to ensured suppression of generation of ringing.

FIG. 52A shows another application of a delay circuit according to thefifth embodiment of the present invention. The output control circuit ofFIG. 52A includes a structure similar to that of FIG. 36. In FIG. 52A,the inverter circuits shown in the previous FIGS. 47-49 are applied toinverter circuits 251-254 in delay circuit 160 a. More specifically, indelay circuit 160 a, the delay time is increased in an operationcondition where the driving capability of the MOS transistor is great.The remaining structure is similar to that of the output control circuitof FIG. 36. Then, the output of the output control circuit of FIG. 52Awill be described with reference to FIG. 52B.

First, output permission signal OEM is pulled to a high level. Here,internal readout data signal ZDD still remains at a low level. This isan operation mode in which an invalid data signal is output. In responseto a rise of output permission signal OEM, the potential of node N1 isdriven to a high level, whereby drive transistor 1 a of a low currentdriving capability is turned on. Therefore, output node 6 is chargedgently.

Then, the output of delay circuit 160 a is pulled up to a high level. Inresponse, the output of AND circuit 90 a is driven to a high level, toturn on drive transistor 1 b via node N31 a. When the output of delaycircuit 160 a attains a high level, the on-timing is delayed when powersupply voltage Vcc takes a value approximate to upper limit value Vcmxor when ambient temperature T takes a value approximate to lower limitvalue Tamn than in the opposite case. Therefore, the on timing of drivetransistor 1 b of a great current driving capability is delayed in anoperating environment where the current driving capability of an MOStransistor is increased. Therefore, increase in the potential of outputnode 6 can be suppressed reliably, and the potential amplitude of outputnode 6 can be reduced to suppress generation of ringing. By setting thedelay time of delay circuit 160 a at an appropriate value, the time ofdrive transistor 1 b turned on can be set to substantially 0 in anoperating environment where the current driving capability of the MOStransistor is increased.

When only a valid data signal is output, the potential of node N1attains a low level, and drive transistors 1 a and 1 b are not turnedon. Therefore, generation of ringing can be reliably preventedregardless of the operating environment.

FIG. 53A shows an application of an inverter circuit of the fifthembodiment according to another structure. Referring to FIG. 53A,inverter circuits 261-264 of the fourth embodiment are used for delaycircuit 12 to drive drive transistor 2 b in order to discharge outputnode 6 to the level of the ground potential. The delay time of delaycircuit 12 is reduced when power supply voltage Vcc takes a valueapproximate to lower limit value Vcmn or ambient temperature T takes avalue approximate to upper limit value Tamx. The remaining structure issimilar to the structure of the output control circuit shown in FIGS. 7and 8. The operation of the output control circuit of FIG. 53A will bedescribed with reference to FIG. 53B.

First, output permission signal OEM is pulled up to a high level. Then,internal readout data signal ZDD is pulled up to a high level. As aresult, the potential of node N2 is driven to a high level, and then theoutput of delay circuit 12 is pulled up to a high level. In response toa rise of the output of delay circuit 12, drive transistor 2 b of agreat current driving capability is turned on via AND circuit 8. Delaycircuit 12 has the delay time increased in an operating environmentwhere the current driving capability of the MOS transistor is great.Therefore, in an operating environment where the current drivingcapability of drive transistor 2 b is great, the on-timing of drivetransistor 26 is delayed, so that it is turned on after the potential ofoutput node 6 is reduced to a subsequent low level by drive transistor 2a. Therefore, even when output node 6 is discharged to the level ofground potential with a great current driving capability, no ringing isgenerated, and an output data signal Q is obtained.

In an operating environment where the current driving capability of theMOS transistor is small, the on timing of drive transistor 2 b isincreased. In this case, since the current driving capability of drivetransistor 2 b is made relatively low, the potential of output node 6 isnot discharged so speedily, even when the transistor is turned on at arelatively early timing. Therefore, an output data signal Q can beobtained stably with no generation of ringing.

In an operating environment where the current driving capabilities ofMOS transistors 2 a and 2 b are made low, the on timing of drivetransistor 2 b is advanced. Therefore, the potential of data signal Q ofa low level provided from output node 6 is ascertained at a relativelyhigh speed. Therefore, the access time will not be increased even whenthe operating environment (operating condition) is degraded. Therefore,an output data signal can be output stably at high speed.

When an invalid data signal is not output, internal readout data signalZDD is pulled up to a high level prior to output permission signal OEM.In this case, only the potential of node N2 rises to high level inresponse to the rise of output permission signal OEM to a high level,and the change in the delay time of delay circuit 12 is similar to thatdescribed above. Therefore, an output data signal can be provided stablyand speedily even when only this valid data signal is output.

A structure for generating first and second control voltages will bedescribed hereinbelow.

FIG. 54 shows a structure of a control voltage generation unit.Referring to FIG. 54, a control voltage generation unit includes a VREF1generation circuit 250 for generating a constant reference voltage VREF1independent of the operating temperature and power supply voltage, aVREF2 generation circuit 251 for generating a reference voltage VREF2depending upon power supply voltage and ambient temperature (operatingtemperature), and differential amplify circuits 252 and 253 foramplifying differentially first reference voltage VREF1 from VREF1generation circuit 251 and second reference voltage REF2 from VREF2generation circuit 251. Second control voltage VP is generated fromdifferential amplify circuit 252, and first control voltage VN isgenerated from differential amplify circuit 253. Differential amplifycircuit 252 receives first reference voltage VREF1 at its positive inputand second reference voltage VREF2 at its negative input. Differentialamplify circuit 253 receives second reference voltage VREF2 at itspositive input, and first reference voltage VREF1 at its negative input.First and second control voltages VP and VN having voltage andtemperature dependent characteristics opposite to each other aregenerated by differential amplify circuits 252 and 253. The structure ofeach component will be described.

FIGS. 55A and 55B show characteristics of first reference voltage VREF1and a specific structure of VREF1 generation circuit. As shown in FIG.55A, first reference voltage VREF1 is a constant voltage independent ofpower supply voltage and operating temperature. Referring to FIG. 55B,VREF1 generation circuit 250 includes a constant current source 260provided between a power supply potential node and output node 264, andtemperature compensated constant voltage diode 261 provided betweenoutput node 264 and the ground potential node. Temperature compensatedconstant voltage diode 261 includes a PN diode 262 connected in aforward direction from output node 264, and a Zener diode 263 providedin a reverse direction between PN diode 262 and the ground potentialnode. Zener diode 263 has a positive temperature coefficient, and PNdiode 262 has a negative temperature coefficient. By virtue of theopposing temperature coefficients of diodes 262 and 263, the temperaturedependency on the Zener voltage generated by Zener diode 263 iscompensated for to provide a constant voltage irrespective of theoperating temperature.

Zener diode 263 exhibits a Zener breakdown to generate a constant Zenervoltage when a voltage greater than the Zener voltage is applied in abackward direction. In this case, a voltage of the sum of the Zenervoltage by Zener diode 263 and the forward voltage drop of PN diode 262is generated at output node 264. Since the forward voltage drop of PNdiode 262 and the Zener voltage of Zener diode 263 have negative andpositive temperature coefficients, a constant voltage can be generatedat output node 264 independent of the ambient temperature.

As to constant current source 260 shown in FIG. 55B, various circuitconfigurations of generating a constant current independent of a powersupply voltage and operating temperature are known in the field ofanalog integrated circuits. Such circuits can be employed. A constantreference voltage VREF1 applied by temperature compensated Zener diode260 can similarly be generated by connecting a resistor having a highresistance (so large that the temperature dependent characteristics canbe neglected) between output node 264 and the power supply potentialnode instead of constant current source 260.

It is appreciated from FIGS. 56A and 56B that second reference voltageVREF2 has a negative dependent characteristic with respect to the powersupply voltage and a positive dependent characteristic with respect tothe operating temperature (ambient temperature).

Referring to FIG. 56C, VREF2 generation circuit 251 includes a constantcurrent source 271 provided between the power supply potential node andoutput node 275, an n channel MOS transistor 272 provided between outputnode 275 and node 276, and a resistor 273 provided between node 276 andthe ground potential node. The temperature dependency of resistancevalue R of resistor 273 is set sufficiently greater than the temperaturedependent characteristic of constant current source 271 and thetemperature dependent characteristic of the ON resistance of MOStransistor 272. Resistance R of resistor 273 is set slightly greaterthan the ON resistance of MOS transistor 272. Resistor 273 is formed ofpolysilicon or a diffused resistor having ions of relatively highconcentration implanted, and has a positive temperature coefficient. Theoperation of VREF2 generation circuit 251 will now be described.

A current independent of constant power supply voltage Vcc and ambienttemperature is supplied from constant current source 271. By thisconstant current from constant source 271, reference voltage VREF2determined by the sum of ON resistance R (272) of MOS transistor 272 andresistance R (273) of resistor 273 is generated at output node 275. Whenpower supply voltage Vcc is increased to the level of upper limit valueVcmx, the conductance of MOS transistor 272 is increased, i.e.resistance R (272) is reduced. Therefore, reference voltage VREF2appearing on output node 275 is lowered. More specifically, secondreference voltage VREF2 includes a negative power supply voltagedependent characteristics.

An increase of ambient temperature T causes resistance R (273) ofresistor 273 to be increased, and second reference voltage VREF2 risesfrom output node 275. Here, although the ON resistance R (273) of MOStransistor 272 changes depending upon ambient temperature T, the changeis small enough to be neglected in comparison with the temperaturedependent characteristics of resistor 273. Therefore, second referencevoltage VREF2 has a positive dependent characteristics with respect toambient temperature T.

A constant current source circuit independent of power supply voltageand ambient temperature well known in the field of analog integratedcircuits can be used as constant current source 271 shown in FIG. 56C.

Instead of constant current source 271, a structure may be employedwhere a resistor having a positive temperature coefficient and aresistor having a negative temperature coefficient are provided inparallel between the power supply potential node and output node 275. Asto the resistors having positive and negative temperaturecharacteristics, a resistor called a thermistor can be used.

FIGS. 57A and 57B show the generation manner of first control voltage VNand second control voltage VP, respectively. As shown in FIG. 54,differential amplify circuit 251 receives first reference voltage VREF1at its positive input and second reference voltage VREF2 at its negativeinput. First reference voltage VREF1 is constant. When the differencebetween first and second reference voltages VREF1 and VREF2 becomesgreater, second reference voltage VP is amplified by differentialamplifier circuit 252 to have the potential increased (refer to FIG.57A). More specifically, second reference voltage VREF2 is lowered whenpower supply voltage Vcc increases. Therefore, the difference(VREF1−VREF2) is increased to result in the boosting of second controlvoltage VP. When operating temperature T increases, second referencevoltage VREF2 is boosted. In this case, the difference (VREF1−VREF2)becomes smaller according to increase in the temperature. Therefore, thesecond control voltage VP is reduced. Therefore, second control voltageVP is generated having the power supply voltage and ambient temperaturedependent characteristics shown in FIG. 57A.

Differential amplify circuit 253 shown in FIG. 54 receives secondreference voltage VREF2 at its positive input and first referencevoltage VREF1 at its negative input. Therefore, first control voltage VNhaving characteristics opposite to that of second control voltage VP canbe generated as shown in FIG. 57B.

As to differential amplify circuits 252 and 253, a structure havingconstant amplify characteristics independent of the power supply voltageand ambient temperature well known in the field of analog integratedcircuits can be used. Since the operation characteristics ofdifferential amplify circuits 252 and 253 are independent of the powersupply voltage and ambient temperature, first and second controlvoltages VN and VP can be adjusted according to the power supply voltageand ambient temperature.

Although not particularly described, first and second control voltagesVN and VP have the voltage level set to an appropriate value within avoltage region in which an MOS transistor is operated at a triplole tube(non-linear) region as shown in FIGS. 47B and 48B.

It can be considered that the Zener voltage of Zener diode 263 is higherthan the normal operation power supply voltage (for example 5 volts) inthe structure of FIG. 55B. In such a case, a boosting circuit forboosting a word line, for example, is provided if the device utilizingthis circuit is a semiconductor memory device. By boosting operatingpower supply voltage Vcc by such a boosting circuit, a constantreference voltage VREF1 can be generated from the temperaturecompensated Zener diode.

When the Zener voltage of Zener diode 263 is low and has a negativetemperature characteristic, a resistor having a positive temperaturecoefficient (for example a diffused resistance having a sufficientlyhigh impurity concentration) may be used instead of PN diode 262.

FIG. 58 shows the operating power supply voltage and ambient temperaturedependent characteristic of an inverter circuit according to amodification of the fifth embodiment. Referring to FIG. 58, theoperating power supply voltage Vcc (DELAY) of the inverter circuit islowered when an external power supply voltage is increased, andincreased as ambient temperature is raised. The voltage and temperaturedependent characteristics shown in FIG. 58 are similar to those of thecontrol voltage VN shown in FIG. 45. The only difference is thatoperating power supply voltage Vcc (DELAY) is generated from an externalpower supply voltage. A structure for generating a power supply voltageVcc (DELAY) of FIG. 58 is shown in FIG. 59A.

As shown in FIG. 59A, a structure for generating power supply voltageVcc (DELAY) is formed by a differential amplify circuit 290 receivingfirst reference voltage VREF1 at its negative input and third referencevoltage VREF3 at its positive input. Power supply voltage Vcc (DELAY)generated from differential amplify circuit 290 is applied to the powersupply potential voltage node of inverter circuit 291.

Third reference voltage VREF3 is generated by a circuit configurationsimilar to that shown in FIG. 56C. The only difference is that powersupply voltage Vcc is substituted with external power supply voltageext.Vcc.

In this case, power supply voltage Vcc (DELAY) has the voltage andambient temperature dependent characteristics similar to those of firstcontrol voltage VN shown in FIG. 45. Operating power supply voltage Vcc(DELAY) is lowered as external power supply voltage ext.Vcc approachesthe upper limit value, and increases as ambient temperature isincreased. Therefore, the operating speed of inverter circuit 291 isdegraded in a region near the upper limit value of the external powersupply voltage or the lower limit value of the ambient temperature. (Itis to be noted that the driving capability of the MOS transistor isreduced since the operating power supply voltage is lowered, andinverter circuit 291 is used in a cascade-connected manner, not in onestage.)

As shown in FIG. 59B, when external power supply voltage Vcc is high orambient temperature T is low, the delay time is increased. Thus, aneffect similar to the above-described embodiment can be obtained.

In the fifth embodiment, a structure of an output control circuit whereoutput signal Q at a low level is output is described. However, the sameapplies for an output control circuit where output data signal Q ispulled up to a high level. Furthermore, it can be applied to variousmodifications of the delay circuits of the first to fourth embodiments.

In the fifth embodiment, the delay time of the delay circuit is changedappropriately according to a low level or a high level output datasignal determining the access time.

Embodiment 6

FIG. 60 schematically shows a structure of an output circuit accordingto a sixth embodiment of the present invention. Referring to FIG. 60, avoltage adjuster 301 including exclusive power supply circuits 304 a,304 b, 306 a, 306 b are provided for an output circuit 926 generating anoutput signal Q according to output permission signal OEM and internaldata signal ZDD. Power supply voltage apply circuit 304 a charges powersupply node 300 at a first rate in response to output permission signalOEM. Power supply voltage apply circuit 304 b responds to outputpermission signal OEM to charge power supply node 300 at a second ratefaster than that of the first rate. Ground voltage apply circuit 306 aresponds to output permission signal OEM to discharge ground node 302 ata third rate (may be equal to the first rate). Ground voltage applycircuit 306 b responds to output permission signal OEM to dischargepower supply node 302 to the level of ground potential at a fourth ratehigher than the third rate. The arrangement will be described in detailafterwards. Power supply voltage apply circuit 304 b is activated at atiming behind that of power supply voltage apply circuit 304 a. Groundvoltage apply circuit 306 b is rendered active at a timing behind thatof ground voltage apply circuit 306 a. Power supply node 300 and groundnode 302 form a reference power supply node. Power supply voltage applycircuit 304 a, power supply voltage apply circuit 304 b, ground voltageapply circuit 306 a and ground voltage apply circuit 306 a form areference voltage source.

In activation (activation of output permission signal OEM), outputcircuit 926 operates with the voltages on power supply node 300 andground node 302 as the operating power supply voltage to provide outputsignal Q.

FIG. 61 shows a structure of the output circuit of FIG. 60. Referring toFIG. 61, output circuit 926 includes an inverter 5 for invertinginternal data signal ZDD, a 2-input AND circuit 3 for receiving outputpermission signal OEM and an output signal of inverter circuit 5, a2-input AND circuit 4 for receiving internal data signal ZDD and outputpermission signal OEM, an n channel MOS transistor 1 rendered conductivein response to an output signal of AND circuit 3 for transmittingvoltage VccQ on power supply node 300 to output node 6, and an n channelMOS transistor 2 rendered conductive in response to an output signal ofAND circuit 4 for transmitting voltage VssQ on ground node 302 to outputnode 6. Each of n channel MOS transistors 1 and 2 forms a drivetransistor. The structure of the output circuit of FIG. 61 is similar toa conventional structure except for that the voltage applied to powersupply node 300 and ground node 302 are adjusted.

FIG. 62 shows a structure of voltage adjuster 301 of FIG. 60. Referringto FIG. 62, voltage adjuster 301 includes inverters 310 and 311 forinverting output permission signal OEM, a delay circuit 312 formed of aneven number stages of inverters (four stages in FIG. 62) for delayingoutput permission signal OEM for a predetermined time T5, a 2-input NANDcircuit 313 for receiving an output signal of delay circuit 312 andoutput permission signal OEM, an inverter 314 for inverting an outputsignal of NAND circuit 313, an n channel MOS transistor 315 responsiveto an output signal of inverter circuit 310 for short-circuiting powersupply node 300 and ground node 302, an n channel MOS transistor 316responsive to an output signal of inverter circuit 310 for transmittingreference voltage VREF to power supply node 300, and an n channel MOStransistor 317 responsive to an output signal of inverter circuit 310for transmitting reference voltage VREF to ground node 302. Referencevoltage VREF takes an intermediate voltage level between power supplyvoltage Vcc and ground voltage GND. When output node 6 (refer to FIG.60) is precharged to the level of an intermediate voltage, referencevoltage VREF may be set to the intermediate voltage level to whichoutput node 6 is precharged.

Voltage adjuster 301 further includes an n channel MOS transistor 318responsive to an output signal of inverter 311 for supplying currentfrom the supply node of power supply voltage Vcc to power supply node300 with a first current driving capability, an n channel MOS transistor320 responsive to an output signal of inverter circuit 314 for supplyingcurrent from the supply node of power supply voltage Vcc to lower supplynode 300 with a current driving capability greater than the firstcurrent driving capability, an n channel MOS transistor 319 responsiveto an output signal of inverter circuit 311 for discharging current fromground node 302 to the supply node of a ground voltage with a thirdcurrent driving capability, and an n channel MOS transistor 321responsive to an output signal of inverter circuit 314 for dischargingcurrent from ground node 302 to the supply node of ground voltage GNDwith a fourth current driving capability greater than the third currentdriving capability. The first and third current driving capability maybe equal to each other. Also the second and fourth current drivingcapability may be equal to each other. The magnitude of the currentdriving capability of MOS transistors 3180-321 is realized by settingthe W/L ratio (channel width/channel length) of the transistor to anappropriate value. The current driving capability is increased ascoefficient β (a constant proportional to W/L) is greater.

According to the structure of FIG. 62, power supply voltage applycircuit 304 a includes MOS transistor 318. Power supply voltage applycircuit 304 b includes MOS transistor 320. Ground voltage apply circuit306 a includes MOS transistor 319. Ground voltage apply circuit 306 bincludes MOS transistor 321. Delay circuit 312, NAND circuit 313 andinverter circuit 314 form a rise delay circuit.

The operation of the circuits shown in FIGS. 61 and 62 will be describedwith reference to the operation waveform diagram of FIG. 63.

When output permission signal OEM falls from an H level to an L level,output circuit 926 is rendered inactive, whereby a cycle of reading outoutput data Q is completed. FIG. 63 shows an example where output signalQ is precharged to the level of an intermediate voltage at inactivationof output circuit 926. A structure is employed where output circuit 926is maintained at an output high impedance state when inactive.

In response to the fall of output permission signal OEM to an L level,the output signal of inverter circuit 310 is pulled up to an H level,and MOS transistor 315-317 are turned on. Power supply node 300 andground node 302 are precharged to the level of reference voltage VREF ofthe intermediate voltage level. Also, the output signal of invertercircuit 311 is driven to an L level, and MOS transistors 318 and 319 areturned off. Similarly, the output signal of NAND circuit 313 is drivento an H level, whereby the output signal of inverter circuit 314 ispulled down to an L level. MOS transistors 320 and 321 are turned off.According to a series of these operations, nodes 300 and 302 areprecharged to the level of reference voltage VREF.

At the next data readout operation, output permission signal OEM ispulled up to an H level. The output signal of inverter circuit 310 isdriven to an L level, whereby MOS transistors 315-317 are turned off.Then, the output signal of inverter circuit 311 is driven to an H level,and MOS transistors 318 and 319 having small current drivingcapabilities are turned on. As a result, power supply node 300 isgradually increased from the level of reference voltage VREF by MOStransistor 318 of a low current driving capability. Similarly, groundnode 302 is gradually discharged towards the level of ground voltage byMOS transistor 319 of a small current driving capability. The voltagelevel is gradually lowered from the intermediate level of referencevoltage VREF.

According to the logic level of internal data signal ZDD, one of MOStransistors 1 and 2 shown in FIG. 62 is turned on. MOS transistor 1 or 2turned on transmits the voltage on the corresponding reference powersupply node (power supply node or ground node) to output node 6(conducts a current flow between a corresponding reference power supplynode and output node 6). By first turning on MOS transistors 318 and 319having low current driving capabilities to gradually increase thepotential of nodes 300 and 302, the voltage on nodes 300 and 302 aretransmitted to output node 6 which is driven gently from the level ofthe intermediate voltage.

When the voltage level of output node 6 arrives at a voltage level whereringing is not generated, the voltage level of nodes 300 and 302 arevaried rapidly. No ringing is generated even when the voltage level ofoutput signal Q is increased suddenly. More specifically, after outputpermission signal OEM is pulled up to an H level and the voltage levelof nodes 300 and 302 are driven sufficiently, the output signal of delaycircuit 312 is pulled up to an H level and the output signal of NANDcircuit 313 is pulled down to an L level, whereby the output signal ofinverter circuit 314 is driven to an H level. MOS transistors 320 and321 having great current driving capabilities are turned on. As aresult, the voltage level of nodes 300 and 302 changes at high speed toarrive at respective levels of power supply voltage Vcc and groundvoltage GND. Thus, the voltage level of output node 6 is driven to thelevel of power supply voltage Vcc or ground voltage GND via drivetransistor 1 or 2, whereby an output signal can be generated speedilyand stably with no generation of ringing.

[Modification 1]

FIG. 64 shows a structure of the components of the first modification ofthe sixth embodiment of the present invention. According to thestructure of FIG. 64, a boosted voltage is supplied from boostingcircuit 325 to MOS transistors 318 and 320 shown in FIG. 62. Boostingcircuit 325 boosts power supply voltage Vcc or external power supplyvoltage ext Vcc to generate a high voltage Vp higher than external powersupply voltage ext Vcc. Power supply voltage VccQ applied to powersupply node 302 can be set to a level sufficiently higher than that ofinternal power supply voltage Vcc. In this case, a signal of an H levelhaving a sufficient voltage level can be output with a margin even wheninternal power supply voltage Vcc is lowered due to power consumption.Thus, even in the case where the difference between VOH (high levelvoltage of output signal) and VOL (low level voltage of output signal)is reduced due to a lower power supply voltage, the loss in output drivetransistor 1 can be compensated for to generate an output signal of asufficiently high voltage level by utilizing boosting circuit 325 shownin FIG. 64. Since the charging operation of power supply node 302 iscarried out in two stages, an output signal having a sufficient voltagelevel stably can be provided at a high speed with no generation ofringing.

FIG. 65 shows a structure of an output circuit employing the boostingcircuit of FIG. 64. Referring to FIG. 65, output circuit 926 includes alevel conversion circuit 327 provided between AND circuit 3 and anoutput drive transistor 1, operating with high voltage Vp from boostingcircuit 325 as one operating power supply voltage for converting the Hlevel of the output signal of AND circuit 3 to the high voltage Vplevel. AND circuits 3 and 4 operate with internal power supply voltageVcc as one operating power supply voltage. As to level conversioncircuit 327, a structure can be employed where p channel MOS transistorshave their gates and drains cross-coupled and receive high voltage Vp attheir sources. An n channel MOS transistor is connected between thedrain of each of the p channel MOS transistors and the ground voltagenode. By using this level conversion circuit 327, power supply voltageVccQ of high voltage Vp level applied to power supply node 302 can betransmitted onto output node 6.

Voltage adjuster 301 also receives high voltage Vp. This is required toboost the output signals of inverters 311 and 314 to the level of highvoltage Vp in the structure shown in FIG. 62. High voltage Vp is appliedto inverters 311 and 314, which output a signal of a high voltage Vplevel. In this case, a level conversion circuit may be provided at theoutput portion of inverters 311 and 314. Alternatively, a structure maybe provided in which inverters 311 and 314 per se include a levelconversion function.

In this case, a structure may be employed in which the voltage appliedto power supply node 300 differs from that applied to level conversioncircuit 327. More specifically, two types of high voltages Vp may beprovided from boosting circuit 312. Level conversion circuit 327converts the level of the output signal of NAND circuit 3 to the higherof the two high voltages. The H level voltages from inverters 311 and314 (refer to FIG. 52) are also converted to the level of the highervoltage. In this case, the lower high voltage level can be transmittedto power supply node 300 with no loss of the threshold voltage of theMOS transistor.

The level conversion circuit is not provided at the output portion ofAND circuit 4 in the structure of FIG. 64. In discharging output node 6,drive transistor 2 is turned on even when the gate potential thereofattains the level of internal power supply voltage Vcc. The voltage ofoutput node 6 is discharged to the level of the voltage on ground node302. If the gate potential of drive transistor 2 attains the level ofinternal power supply voltage Vcc, the conductance is reduced incomparison with the case where high voltage Vp is supplied, so that thedischarging rate of output node 6 is reduced. Therefore, a sudden changein current at initiating a discharging operation of output node 6 can besuppressed to prevent ringing in a more reliable manner. Even when thegate voltage level of drive transistor 2 is sufficiently higher than thelevel of ground node 302 and the voltage VssQ on ground node 302 isdischarged towards the level of ground voltage GND at high speed, thevoltage level of output node 6 can be discharged to the level of groundvoltage GND at high speed according to the high speed discharging.

A structure may be employed where a level conversion circuit is providedbetween the gate of drive transistor 2 and AND circuit 4 to increase thegate potential of drive transistor 2 to a sufficient high level, and thedischarging rate of output node 6 is adjusted only by voltage adjuster301. In the above-described structure, the voltages on power supply node300 and ground node 302 (generically referred to as “reference powersupply node”) are varied in two stages. Alternatively, a structure maybe employed where the voltage on the reference power supply node isvaried over three or more stages.

In this output circuit, a structure may be combinedly employed using aplurality of drive transistors connected in parallel with delay timevariable according to whether an invalid signal is output or not.Furthermore, the structure of output circuit 926 may be applied to allthe previous first to fifth embodiments.

By providing a structure according to a sixth embodiment where thevoltage on a reference power supply node of an output stage transistordriving an output node according to an internal signal has the changingrate varied in a plurality of steps, the voltage change in output node 6can be first impelled gently, and then gradually increased. Therefore, astable output signal can be provided speedily with no ringing.

Embodiment 7

FIG. 66 shows a structure of the main part of an output circuitaccording to a seventh embodiment of the present invention. FIG. 66shows a structure of a voltage adjustment unit for providing theoperating power supply voltages of the output circuit. The structure ofthe output circuit itself is similar to that shown in FIG. 61.

The voltage adjustment unit of FIG. 66 is different from voltageadjuster 301 shown in FIG. 60 in the structure as set forth in thefollowing. According to the structure of FIG. 66, and n channel MOStransistors 328 responsive to an output signal of inverter circuit 311transmits a voltage Vccp between reference voltage VREF and power supplyvoltage Vcc to power supply nodes 300. An n channel MOS transistor 330provided parallel to MOS transistor 328 responds to an output signal ofinverter circuit 314 to transmit power supply voltage Vcc to powersupply node 300. An n channel MOS transistor 329 coupled to ground node302 responds to an output signal of inverter circuit 311 to transmit avoltage Vbsg of a level closer to intermediate reference VREF than toground voltage GND to ground node 302. An n channel MOS transistor 331responds to an output signal of inverter circuit 314 to transmit groundvoltage GND to ground node 302. The remaining structure is similar tothat shown in FIG. 62.

The W/L ratio of the channel width to the channel length of MOStransistors 328 and 330 may be identical. Alternatively, as shown inFIG. 62, the ratio of the channel width to the channel length (orcoefficient β) of MOS transistor 328 may be set smaller than that of MOStransistor 330. Also, the W/L of MOS transistor 329 may be set equal toor smaller than that of MOS transistor 331. The operation thereof willbe described briefly.

The operation of the output circuit is similar to that shown in FIG. 61.In a standby state, the output signal of inverter circuit 310 attains anH level, and MOS transistors 315, 316, and 317 are turned on. Nodes 300and 302 are precharged to the level of reference voltage VREF. Here, theoutput signals of inverter circuits 311 and 314 are both at an L level(output permission signal OEM is at an L level). MOS transistors 328,330, 321 and 331 are all turned off.

When a data signal is to be read out, output permission signal OEM ispulled up to an H level from an L level, whereby MOS transistors 315-317are all turned off. First, output signal of inverter circuit 311 isdriven to an H level, and MOS transistors 328 and 329 are turned on. ByMOS transistors 328, power supply node 300 is charged to the level ofvoltage Vccp where no ringing is generated. MOS transistors 329 gentlydischarges ground node 302 towards the level of voltage Vbsg where noringing is generated. Then, MOS transistors 330 and 331 are turned on byan output signal of inverter circuit 314, whereby power supply node 300is charged at high speed to the level of power supply voltage Vcc.Ground node 302 is discharged at high speed to the level of groundvoltage GND. When an output signal of a high level is provided from theoutput circuit, the voltage on power supply node 300 is transmitted ontooutput node 6 via drive transistor 1 (refer to FIG. 61). When the outputcircuit provides a signal of a low level, the voltage on ground node 302is transmitted onto output node 6 via drive transistor 2. Therefore, thevoltage change in output node 6 is substantially equal to the change ofthe voltage of power supply node 300 or ground node 302. As a result,output signal Q on output node 6 is driven gently to the level of avoltage where no ringing is generated, and then at high speed to thelevel of power supply voltage or ground voltage. Thus, a stable outputsignal can be provided speedily with no ringing.

MOS transistor 329 may have a ratio of the channel width to channellength of W/L (or coefficient β) similar to that of MOS transistor 331.Since the source voltage Vbsg of MOS transistor 329 is higher than thesource voltage GND of MOS transistor 331, the gate voltage of MOStransistor 329 becomes lower than that of MOS transistor 331, wherebythe conductance of MOS transistor 329 becomes smaller than that of MOStransistor 331. As a result, the current driving capability of MOStransistor 329 is set smaller than the current driving capability of MOStransistor 331.

A p channel MOS transistor may be provided for MOS transistors 318, 320,328 and 330 for charging power supply node 300 shown in FIGS. 62 and 66.Power supply voltage Vcc can be transmitted to power supply node 300with no threshold voltage loss. In the structure of FIG. 66, when pchannel MOS transistors are used instead of n channel MOS transistors328 and 330, the ratio of the channel width to the channel length (orcoefficient β) of these p channel MOS transistors may be equal. This isbecause the current driving capability of the p channel MOS transistorreceiving voltage Vccp at its source is set smaller than that of the pchannel MOS transistor receiving voltage Vcc at its source.

FIGS. 67A and 67B show a structure for generating voltages Vccp andVbsg, respectively of FIG. 66.

Referring to FIG. 67A, a voltage generation circuit includesdiode-connected p channel MOS transistors PM1-PMn connected in seriesbetween the supply node of power supply voltage Vcc and node 332, and aresistor Rp connected between node 332 and the supply node of groundvoltage GND. Resistor Rp has a resistance value greater than the channelresistance of MOS transistors PM1-PMn.

Each of MOS transistors PM1-PMn operates in a diode mode causing avoltage drop by the absolute value of the threshold voltage Vthp.According to the structure shown in FIG. 67A, the voltage of Vcc—n·Vthpis output as voltage Vccp. The number of MOS transistors PM1-PMn areappropriately selected according to the level of voltage Vccp.

Referring to FIG. 67B, a voltage generation unit includes a resistor Rnconnected between the supply node of power supply voltage Vcc and node333, and diode-connected n channel MOS transistors NM1-NMn connected inseries between node 333 and the supply node of ground voltage GND.Resistor Rn has a resistance sufficiently greater than the channelresistance of each MOS transistors NM1-NMn. In this case, MOStransistors NM1-NMn each operate in a diode mode causing a voltage dropby the threshold voltage Vthn. According to the structure shown in FIG.67B, voltage Vbsg appearing on node 33 is n·Vthn (ground voltage GND is0 V).

Voltage Vccp has a value greater than the reference voltage VREF.Voltage Vbsg has a value smaller than reference voltage VREF.

Various reference voltage generation circuits may be used instead of thestructure of the voltage generation circuit shown in FIGS. 67A and 67B.

According to the structure of the seventh embodiment in which the powersupply node and the ground node providing a voltage determining thevoltage level of the output signal of the output circuit are driven intwo steps, and wherein respective currents are supplied in the firststep from the supply sources of voltage Vccp lower than the power supplyVcc and voltage Vbsg higher than ground voltage GND towards the powersupply node and the ground node, the output node of the output circuitcan reliably be driven to a voltage level where no ringing is generateddue to generation of these voltages all the power supply and groundnodes stably. Then, the output node can be driven speedily to the levelof power supply voltage Vcc or ground voltage GND to provide a stableoutput signal with no ringing.

Since a voltage level of no ringing can be set by voltages Vccp and Vbsgaccording to the structure of the seventh embodiment, it can be reliablyprevented that the output node is charged or discharged at high speedwhen the voltage level of the output node has not yet changedsufficiently. Thus, generation of ringing can be reliably suppressed.

Embodiment 8

Referring to FIG. 68, similar to the previous embodiment, an outputcircuit 926 of the eighth embodiment of the present invention includesan inverter circuit 5 for inverting internal data signal ZDD, an ANDcircuit 3 for receiving output permission signal OEM and an outputsignal of inverter circuit 5, an AND circuit 4 for receiving outputpermission signal OEM and internal data signal ZDD, a drive transistor 1responsive to an output signal of AND circuit 3 for driving output node6 to the level of voltage VccQ on power supply node 300, and an outputdrive transistor 2 responsive to an output signal of AND circuit 4 fordischarging output node 6 to the level of voltage VssQ on ground node302.

Output circuit 926 further includes a voltage adjuster 340 responsive toa signal applied to node N2 from AND circuit 4 to adjust the voltagelevel on ground node 302. Although only voltage adjuster 340 foradjusting voltage VssQ on ground node 302 is shown in FIG. 68 for thesake of simplification, a voltage adjuster for adjusting voltage VccQ onpower supply node 300 according to the voltage level on node N1 is alsoprovided. The circuit for adjusting voltage VccQ on power supply node300 according to the signal on node N1 is similar in configuration tothat of voltage adjuster 340.

Voltage adjuster 340 includes a driving circuit 350 for determining theabsence/presence of an invalid data output in response to outputdesignating signal DOT and an internal signal on node N2 to adjust thedelay time according to the determination result for providing anactivation signal at an elapse of a predetermined adjusted delay time, a2-input NAND circuit 351 for receiving an output signal of drivingcircuit 350 and an internal signal on node N2, an inverter circuit 352for inverting the output signal of NAND circuit 351, an inverter circuit353 for inverting a signal on node N2, an inverter circuit 354 forinverting an output signal of inverter circuit 353, an n channel MOStransistor 360 having a relatively small current driving capability andrendered conductive in response to an output signal of inverter circuit354 for discharging ground node 302 towards the level of ground voltageGND, and an n channel MOS transistor 365 having a relatively largecurrent driving capability and rendered conductive in response to anoutput signal from inverter circuit 352 for discharging ground node 302to the level of ground voltage GND. Inverter circuits 353 and 354 form abuffer circuit.

Voltage adjuster 340 further includes an inverter circuit 370 forinverting output permission signal OEM, and an n channel MOS transistor375 responsive to an output signal of inverter circuit 370 fortransmitting reference voltage VREF to ground node 302. MOS transistor375 is rendered conductive when output circuit 926 is inactive at an Lperiod of output permission signal OEM, to precharge ground node 302 tothe level of reference voltage VREF.

Driving circuit 350 includes an inverter circuit 381 for invertingoutput designating signal DOT, a 2-input NAND circuit 382 for receivingan internal signal on node N2 and an output signal of inverter circuit381, a 2-input AND circuit 383 for receiving an internal signal on nodeN2 and output designating signal DOT, and a flipflop 384 includingcross-coupled NAND circuits NA23 and NA14 set in response to an outputsignal of NAND circuit 382 and reset in response to an internal signalon internal node N2, an inverter circuit 385 for receiving an outputsignal of NAND circuit NA13 in flipflop 384, a delay circuit 387 fordelaying an output signal of inverter circuit 385 for a predeterminedtime T1, a 2-input NAND circuit 386 for receiving an output signal ofinverter circuit 385 and an output signal of AND circuit 383, a delaycircuit 388 for delaying an output signal of NAND circuit 386 for apredetermined time period T2, and a 2-input NAND circuit 389 forreceiving output signals of delay circuits 387 and 388.

Flipflop 384 includes a function of determining whether a valid datasignal (a signal of an H level) is output or not on internal node N2when output designating signal DOT attains an active state of an Hlevel. The delay time T1 of delay circuit 387 is set longer than delaytime T2 of delay circuit 388.

The structure of driving circuit 350 is substantially similar to thecontrol circuit adjusting the conducting timing of the drive transistor2 shown in FIG. 16. The operation will now be described.

A case where there is no invalid output will be described with referenceto the waveform diagram of FIG. 69. When the internal signal on internalnode N2 is driven to an L or H level, the output signal of invertercircuits 353 and 354 is pulled up to an H level, whereby MOS transistor360 is turned on. By this small current driving capability thereof,voltage VssQ on ground node 302 is discharged from the level ofintermediate voltage VREF to ground voltage GND. Output permissionsignal OEM is already pulled to an H level, whereby MOS transistors 345is turned off. Ground node 302 is isolated from the supply source ofinternal voltage VREF. In contrast, drive transistor 2 is turned on inresponse to an internal signal on internal node N2, whereby output node6 is discharged to the level of voltage VssQ on ground node 302. Thesignal on node N2 is an invalid signal since output designating signalDOT is not pulled up to an H level yet. Therefore, the output signal isan invalid signal until node N2 is driven to an H level. Output node 6is charged by power supply node 300 via drive transistor 1. Flipflop 384is kept reset, and provides an output signal of an L level. When outputdesignating signal DOT is pulled up to an H level from an L level, theoutput signal of NAND circuit 382 is driven to an L level, wherebyflipflop 384 is set. In response, the output signal of inverter circuit385 is pulled down to an L level. Although the output signal of ANDcircuit 383 is pulled up to an H level simultaneously, the output signalof inverter circuit 385 attains an L level, so that the output signal ofNAND circuit 386 maintains an H level. Therefore, the output signal ofdelay circuit 388 maintains an H level.

At an elapse of a predetermined time T1 from the fall of the outputsignal of inverter circuits 385 to an L level, the output signal ofdelay circuit 387 is driven to an L level and the output signal of NANDcircuit 389 is driven to an H level. Here, the internal signal on nodeN2 is already driven to an H level. The input signal of NAND circuit 351is also driven to an H level. The output signal of NAND circuit 351 ispulled down to an L level from the H level, whereby the output signal ofinverter circuit 352 is pulled up to an H level from an L level. As aresult, MOS transistor 365 of a great current driving capability whichwas OFF is turned on, whereby ground node 302 is rapidly lowered to thelevel of ground voltage GND.

As a result, output signal Q on output node 6 is driven to the level ofground voltage GND via drive transistor 2. MOS transistor 365 is turnedon at an elapse of a delay time T1 from the rise of output designatingsignal DOT to an H level. By lengthening this delay time T1, outputsignal Q raised by an invalid data output is gently reduced to thevoltage level where no ringing is generated. Then, the output node canbe lowered to the level of ground voltage GND speedily, whereby a stableoutput signal is provided with no ringing.

An operation of the case where an invalid signal is not output will bedescribed with reference to the operation waveform diagram of FIG. 70.The internal signal on internal node N2 is pulled up to an H levelfollowing the rise of output designating signal DOT to an H level. Whenthe internal signal of node N2 is driven to an H level together withoutput designating signal DOT, the output signal of AND circuit 383 ispulled up to an H level. When the internal signal of internal node N2 isat an L level, the output signal of NAND circuit 382 attains an H levelindependent of the state of output designating signal DOT. Therefore,flipflop 384 maintains a reset state, so that an output signal thereofmaintains an L level. Accordingly, the output signal of inverter circuit385 maintains an H level. Therefore, when the output signal of ANDcircuit 383 is pulled to an H level, the output signal of NAND circuit386 is pulled down to an L level. At an elapse of a predetermined timeT2, the output signal of delay circuit 388 is pulled down to an L level.As a result, the output signal of NAND circuit 389 is pulled up to an Hlevel from an L level.

In response to an internal signal driven to an H level on internal nodeN2, MOS transistor 360 is turned on by inverter circuits 353 and 354.MOS transistor 375 is already turned off, and voltage VssQ on groundnode 302 is discharged to the level of ground voltage GND via MOStransistor 360 to be lowered gently. As a result, drive transistor 2discharges output signal Q on output node 6 according to voltage VssQ onground node 302. Therefore, the potential change of output signal Q onoutput node 6 is gentle, and no ringing is generated on output node 6.At an elapse of a delay time T2 from the rise of the internal signal ofinternal node N2 to an H level, the output signal of NAND circuit 351 isdriven to an L level and the output signal of inverter circuit 352 isdriven to an H level, whereby MOS transistor 365 of a great currentdriving capability is turned on. As a result, voltage VssQ on groundnode 302 lowered to a voltage level where no ringing is generated isdischarged speedily to the level of ground voltage GND by MOS transistor365 of a great current driving capability. Drive transistor 2 dischargesthe voltage on output node 6 to the level of the voltage on ground node302. In this case, although output signal Q on output node 6 is loweredspeedily, a stable output signal with no ringing is provided from outputnode 6 since it is already lowered to a voltage level where no ringingwill be generated.

By adjusting the timing at which drive transistor 365 driving groundnode 302 attains on-state according to absence/presence of an invalidsignal output, the voltage on output node 6 can be reliably dischargedto the level where no ringing is generated and then to the groundvoltage level. Therefore, a stable output signal with no ringing can begenerated regardless of absence/presence of an invalid signal.

In the structure shown in FIG. 68, MOS transistor 360 may be connectedto receive a voltage Vbsg higher than the ground voltage level GND asshown in FIG. 66. As to output circuit 926, a structure where theon-timing of an output node driving transistor having a great currentdriving capability is changed in response to absence/presence of aninvalid output may be provided as shown in the previous FIGS. 23, 25,27, 29 and 31.

As to the structure of driving circuit 350 in the voltage adjuster shownin FIG. 68, a structure where the on-timing of MOS transistor 360 isdifferentiated according to absence/presence of an invalid signal outputmay be employed. The structure shown in FIGS. 23, 25, 27, 29 and 31 maybe applied to this control circuit.

According to the structure of the eighth embodiment of the presentinvention, a plurality of transistors having different current drivingcapabilities are provided with respect to a reference power supply nodeof the output circuit, and the on-timing of a transistor of a greatcurrent driving capability is differentiated according toabsence/presence of an invalid output. Therefore, an output signal of noringing can be output at high speed regardless of absence/presence of aninvalid output.

Embodiment 9

Referring to FIG. 71, an output circuit 926 of the ninth embodimentincludes a delay circuit 401 for delaying a signal on internal node N2for a predetermined time, a delay circuit 402 for delaying an outputsignal of delay circuit 401 for a further predetermined time, a NANDcircuit 404 for receiving a signal on internal node N2 and an outputsignal on delay circuit 401, a 2-input AND circuit 706 for receiving aninternal signal on internal node N2 and an output signal of delaycircuit 402, a drive transistor 2 e formed of an n channel MOStransistor rendered conductive in response to the internal signal ofinternal node N2 for discharging output node 6 to the level of groundvoltage GND, a drive transistor 2 f formed of an n channel MOStransistor rendered conductive in response to an output signal of ANDcircuit 404 for driving output node 6 to the level of ground voltageGND, and a drive transistor 2 g formed of an n channel MOS transistorrendered conductive in response to an output signal of AND circuit 406.

Similar to the previous embodiments, output circuit 926 further includesan inverter circuit 5 for inverting internal data signal ZDD, an ANDcircuit 3 for receiving output permission signal OEM and an outputsignal of inverter circuit 5, a drive transistor 1 formed of an nchannel MOS transistor rendered conductive in response to an outputsignal of AND circuit 3 for charging output node 6 to the level of powersupply voltage Vcc, and an AND circuit 4 responsive to output permissionsignal OEM and internal data signal ZDD for turning on drive transistor2 e. Drive transistors 2 e, 2 f and 2 g have threshold voltages Vth1,Vth2, and Vth3, respectively, and receive bias voltages VBB1, VBB2, andVBB3, respectively, to their well regions (or substrate regions).

Threshold voltages Vth1, Vth2 and Vth3 satisfy the relationship of:Vth1>Vth2>Vth3>0

Substrate bias voltages VBB1, VBB2 and VBB3 satisfy the relationship of:VBB1<VBB2<VBB3<0

With an increase of the threshold voltage of the n channel MOStransistor, the gate potential is effectively lowered when the same gatevoltage is applied, whereby the conductance is reduced. Therefore, whenthe same voltage of H level is applied to drive transistors 2 e, 2 f and2 g, the conductance is increased in the order of drive transistors 2 e,2 f and 2 g. Similarly, as the absolute value of the substrate biasvoltage is increased, the absolute value of the threshold voltage of theMOS transistor is increased. Similarly, due to this substrate biasvoltage, the substrate bias effect is reduced to increase theconductance in the order of drive transistors 2 e, 2 f and 2 g. It isassumed here that drive transistors 2 e, 2 f and 2 g have the same size.

In operation, when the internal signal on internal node N2 is pulled upto an H level, drive transistor 2 e is turned on, whereby output node 6is discharged to the level of ground voltage GND. Drive transistor 2 ehas the threshold voltage Vth1 set to a maximum value and the substratebias voltage set to the minimum value to increase substrate bias effect.Therefore, output node 6 is discharged to the level of ground voltageGND with a relatively small current driving capability. Then, when theoutput signal of delay circuit 401 is pulled up to an H level, drivetransistor 2 f is turned on. Drive transistor 2 f has a thresholdvoltage Vth2 and a substrate bias voltage VBB2 of a middle level, sothat output node 6 is discharged to the level of ground potential GNDwith a relatively great current capability. Then, when the output signalof delay circuit 402 is pulled up to an H level, the output signal ofAND circuit 406 is driven to an H level, whereby drive transistor 2 g isturned on. Drive transistor 2 g has a substrate bias set to the minimumvalue and threshold voltage VTH3 set to the minimum value. Therefore,output node 6 is discharged to the level of ground voltage GND with agreat current driving capability. As a result, the voltage of outputnode 6 lowered by drive transistors 2 e and 2 f to the voltage levelwhere no ringing is generated is further discharged at high speed to thelevel of ground voltage GND via drive transistor 2 g.

By differentiating the level of substrate bias voltage VBB (VBB1-VBB3)and threshold voltage Vth (Vth1-Vth3) to differ the current drivingcapability of each drive transistor, output node 6 is discharged in arelatively mild manner at the initial stage, and then to the level ofground voltage GND at high speed using a drive transistor of a greatcurrent driving capability when the voltage level is reduced to a levelwhere no ringing is generated. Thus, a stable output signal can beprovided speedily with no ringing.

[Modification 1]

Referring to FIG. 72 showing a modification of the output circuit of theninth embodiment, voltage VssQ from voltage adjuster 301 b is applied toground node 302 forming the common source of drive transistors 2 e, 2 fand 2 g discharging output node 6. Drive transistors 2 e, 2 f and 2 gand delay circuits 401 and 402 are similar to those shown in FIG. 71.Corresponding portions have the same reference characters allotted.Voltage adjuster 301 b responds to output permission signal OEM toconvert the level of output voltage VssQ from the level of referencevoltage VREF to the level of ground voltage GND. The structure of thisvoltage adjuster is similar to that shown in FIGS. 62 and 66.

Referring to FIG. 72, the output circuit further includes drivetransistors 1 e, 1 f and 1 g each formed of an n channel MOS transistorprovided in parallel between power supply node 300 and output node 6.Drive transistor 1 e conducts in response to a signal on internal nodeN1. Drive transistor 1 f conducts in response to an output signal ofdelay circuit 403 delaying a signal on internal node N1 for apredetermined time period. Drive transistor 1 g conducts in response toan output signal of delay circuit 404 which further delays the outputsignal of delay circuit 403. Drive transistors 1, 1 f, and 1 g havedifferent threshold voltages and different substrates bias voltages. InFIG. 72, drive transistors 1 e, 1 f and 1 g are shown to have thresholdvoltages and bias voltages of a level identical to those of drivetransistors 2 e, 2 f and 2 g for discharging output node 6. However, thepresent invention is not limited to such values, and may be set to anarbitrary value as long as a drive transistor that is precedingly turnedon has a greater threshold voltage and a deeper substrate bias. Delaycircuits 403 and 404 have a delay time similar to those of delaycircuits 401 and 402, respectively.

Voltage VccQ from voltage adjuster 301 a is applied to power supply node300. Voltage adjuster 301 a is activated in response to outputpermission signal OEM to adjust output voltage VccQ from the level ofreference voltage VREF. Similar to voltage adjuster 301 b, voltageadjuster 301 a has a structure shown in FIG. 62 or 66.

In general, a current (drain current) Ids flowing from the drain to thesource of an MOS transistor is represented by the following equation:Saturated Region: |Vds|≧|Vgs−Vth|;Ids=(Vgs−Vth)²Nonsaturated Region: |Vds|i<|Vgs−Vth|:Ids=A{(Vgs−Vth)Vds−(Vds ²/2)},where Vds indicates drain-source voltage, Vgs indicates gate-sourcevoltage, and Vth indicates threshold voltage.

Drain current Ids is greatly affected by threshold voltage Vth asgate-source voltage Vgs is lowered in either case of a saturated regionor nonsaturated region. More specifically, when power supply voltage Vccis lowered and the amplitude of the output signal of output node 6 isreduced, the changing rate of the signal on output node 6 can beadjusted sufficiently by threshold voltage Vth. Similarly, the thresholdvoltage Vth has the relation of:Vth=A+B(C+|VBB|)^(1/2)More specifically, threshold voltage Vth has a greater absolute valuefor a greater absolute value of substrate bias voltage VBB. In the casewhere the power supply voltage is lowered, the influence of substratevoltage bias VBB is overlaid on threshold voltage, so that the change ofthe voltage level of output node 6 can be adjusted. The advantages setforth in the following are obtained when the voltage of power supplynodes 300 and ground node 302 are adjusted using voltage adjusters 301 aand 301 b as shown in FIG. 72.

At the initial stage where output permission signal OEM is activated,voltage VssQ applied to ground node 302 is at a level higher than groundvoltage GND. In this case, drive transistors 2 e, 2 f and 2 g have theirsource potentials increased, which effectively lowers the gate voltages.Specifically, gate voltage Vgs is reduced. In this case, the influenceof threshold voltage Vth is increased, as shown in the above equation,whereby the effect of the substrate bias voltage is increased. When thevoltage level of output node 6 is reduced to a level where no ringing isgenerated, the voltage on ground node 302 is also set to the level ofground voltage GND. Therefore, the gate-source voltage Vgs of drivetransistors 2 e-2 g takes a sufficiently great value. In this case, theinfluence of threshold voltage Vth is relatively low, so that outputnode 6 can be discharged to the level of ground voltage GND at highspeed. Therefore, by varying the voltage on ground node 302 in a stepmanner, the current driving capability of a drive transistor can beadjusted taking advantage of the substrate bias voltage and thresholdvoltage effectively.

The same applies to drive transistors 1 e, 1 f and 1 g for chargingoutput node 6. When the voltage on power supply node 300 is relativelylow, only drive transistor 1 e is turned on. In the drain (conductiveregion connected to power supply node 300) of drive transistor 1 e, adepletion layer is relatively wide since the junction of the impurityregion and the substrate region attains a relatively weak reverse biasstate. Therefore, the drain electric field is so small that a flow ofdrain current is suppressed, and the drain current has substrate biasdependency. Therefore, the drain current can be suppressed effectively,so that the current can be supplied from power supply node 300 to outputnode 6 gently. When voltage VssQ on power supply node 300 takes asufficiently high value, the junction of the drain region and thesubstrate region in each of drive transistors 1 e-1 g attains asufficiently reversed bias state. The depletion layer is narrow enough,so that a drain current is conducted easily. In this case, the biasvoltage dependency is not degraded, and a relatively large drain currentcan be supplied. In this state, drive transistor 1 e is turned on.Therefore, drive transistors 1 e-1 g can have well adjusted currentdriving capabilities by adjusting the threshold voltage and the biasvoltage to appropriate values. By using a plurality of drive transistorswith different substrate bias and threshold voltages in combination witha circuit that adjusts voltages VssQ and VccQ on ground node 302 andpower supply node 300, an output circuit can be obtained thateffectively suppresses generation of ringing.

In the structure shown in FIGS. 71 and 72, ringing in an output signalcan be suppressed more effectively, by combining a structure where theON-timings of drive transistors 1 e and 2 e are controlled according toabsence/presence of an invalid output.

In accordance with the structure of the ninth embodiment where aplurality of transistors having different substrate bias and thresholdvoltages are provided in parallel between an output node and a referencepower supply node, which are turned on at different timings. These drivetransistors have different current driving capabilities, and an outputcircuit can be obtained that provides a stable output signal speedilywhile suppressing ringing effectively.

Embodiment 10

FIGS. 73A and 73B show a structure and operation of an output circuitaccording to a tenth embodiment of the present invention. In FIG. 73A,an n channel MOS transistor 412 rendered conductive in response to anoutput signal of a rise delay circuit 410 for delaying a signal oninternal node N2 for a predetermined time period, and a resistanceelement 414 parallel to MOS transistor 412 are provided between outputnode 6 and drive transistor 2 discharging output node 6. Resistanceelement 414 has a current limiting function. The remaining structure issimilar to that of the previous embodiments. More specifically, theoutput circuit includes an inverter circuit 5 for inverting internaldata signal ZDD, an AND circuit 3 for receiving output permission signalOEM and an output signal of inverter circuit 5, a drive transistor 1rendered conductive in response to an output signal NOH of AND circuit 3for driving output node 6 to the level of power supply voltage Vcc, anAND circuit 4 for receiving output permission signal OEM and internaldata signal ZDD, and a drive transistor 2 rendered conductive inresponse to output signal NOL of AND circuit 4. The operation of theoutput circuit of FIG. 73A will now be described with reference to theoperation waveform diagram of FIG. 73B.

When output permission signal OEM attains an L level, output signal NOLof AND circuit 4 attains an L level, and drive transistor 2 is turnedoff. Also, output signal A of rise delay circuit 410 attains an L level,and MOS transistor 412 is turned off.

When output permission signal OEM and internal data signal ZDD bothattain an H level, output signal NOL from AND circuit 4 is driven to anH level, whereby drive transistor 2 is turned on. However, output signalA of rise delay circuit 400 is still at an L level, and MOS transistor412 is OFF. Under this state, output node 6 is discharged to the levelof ground voltage GND via resistance element 414 and drive transistor 2.In this case, output node 6 is discharged in a relatively mild manner bythe current limiting function of resistance element 414.

At an elapse of a predetermined time T6 from the rise of output signalNOL of AND circuit 4 to an H level, output signal A of rise delaycircuit 410 is pulled up to an H level. As a result, MOS transistor 412is turned on, so that resistance element 414 is short-circuited. The ONresistance (channel resistance) of MOS transistor 412 is preselected toa sufficiently low value in comparison with the resistance value ofresistance element 414. Therefore, output node 6 is discharged at highspeed to the level of ground voltage GND via MOS transistor 412 anddrive transistor 2. When MOS transistor 412 is turned on, the voltagelevel of output node 6 is lowered to the level where no ringing isgenerated. Therefore, an output signal of no ringing is provided atoutput node 6 even when output node 6 is discharged speedily to thelevel of ground potential GND.

Delay circuit 410, MOS transistor 412 and resistance element 414 shownin FIG. 73A may be provided for drive transistor 1.

[Modification 1]

FIGS. 74A and 74B show a structure and operation of a first modificationof the output circuit of the tenth embodiment. Referring to FIG. 74A,output circuit 926 includes an inverter circuit 5 for inverting internaldata signal ZDD, an AND circuit 3 for receiving an output signal ofinverter circuit 5 and an output permission signal OEM, a drivetransistor 1 rendered conductive in response to an output signal NOH ofAND circuit 3 for driving output node 6 to the level of power supplyvoltage Vcc, an AND circuit 4 for receiving output permission signal OEMand internal data signal ZDD, and a drive transistor 2 h renderedconductive in response to an output signal NOL1 of AND circuit 4 fordischarging output node 6 to the level of ground voltage GND.

Output circuit 926 further includes a rise delay circuit 420 fordelaying the rise of output signal NOL1 of AND circuit 4 for apredetermined time, a rise delay circuit 422 for delaying the rise ofoutput signal NOL2 of rise delay circuit 420 for a further predeterminedtime period, an MOS transistor 424 having one end connected to outputnode 6, and rendered conductive in response to output signal A of risedelay circuit 422, a resistance element 426 connected in parallel to MOStransistor 424, and a drive transistor 2 i rendered conductive inresponse to an output signal NOL2 of rise delay circuit 420 for couplingresistance element 426 to ground voltage GND. The channel width of drivetransistor 2 h is set smaller than that of drive transistor 2 i. Thecurrent driving capability of drive transistor 2 h is set smaller thanthat of drive transistor 2 i. The channel resistance (ON resistance) ofMOS transistor 424 is set sufficiently smaller than the ON resistance ofresistance element 426. The operation of the output circuit of the FIG.74A will be described with reference to the operation waveform diagramof FIG. 74B.

When at least one of output permission signal OEM and internal datasignal ZDD is at an L level, output signal NOL1 of AND circuit 4maintains an L level. Drive transistors 2 h and 2 i are both turned off,so that output node 6 is not discharged.

When output permission signal OEM and internal data signal ZDD bothattain an H level, output signal NOL1 of AND circuit 4 is driven to an Hlevel. In response, drive transistor 2 h is turned on. Output node 6 isdischarged gently towards the level of ground voltage GND by drivetransistor 2 h of a relatively low current driving capability. At anelapse of a delay time T7 of rise delay circuit 420 from the rise ofsignal NOL1 to an H level, output signal NOL2 of rise delay circuit 420is pulled up to an H level, whereby drive transistor 2 i is turned on.Thus, output node 6 is discharged to the level of ground voltage GND viaresistance element 426 and drive transistor 2 i. According to thecurrent limiting function of resistance element 426, output node 6 isdischarged mildly to the level of ground voltage.

Then, at an elapse of delay time T8 of rise delay circuit 422 from therise of signal NOL2 to an H level, output signal A of rise delay circuit422 is pulled up to an H level, whereby MOS transistor 424 is turned on.The channel resistance (ON resistance) of MOS transistor 424 is presetsufficiently smaller than the resistance value of resistance element426. Therefore, output node 6 is discharged at high speed to the levelof ground voltage GND by a great current driving capability of drivetransistor 2 i. Since output node 6 is discharged at high speed to thelevel of ground voltage after being lowered to the level of voltagewhere ringing is not generated, an output signal can be generated athigh speed with no ringing. The lowering rate of the voltage level ofoutput node 6 is sequentially increased in three stages, and thedischarging rate of output node 6 is increased at the time when there isno possibility of ringing. Therefore, an output signal can be generatedmore speedily with no ringing.

The structure of FIG. 74A can also be applied to a structure whereoutput node 6 is charged to the level of power supply voltage Vcc.

As to the structure of the output circuit shown in FIGS. 73A and 74A,voltage VccQ and VssQ may be applied using a voltage adjuster, insteadof power supply voltage Vcc and ground voltage. Furthermore, a structurein which the on timing is differentiated according to absence/presenceof an invalid output can be used for drive transistors 1 and 2 h.

According to the tenth embodiment of the present invention in which theoutput node is first driven to the voltage level of the reference powersupply node using a resistance element, and then driven speedily to thelevel of the reference power supply node after the resistance element isshorted, the output node is driven in a more gentle manner by thecurrent limiting function of the resistance element when there is apossibility of ringing, followed by a drive of the output node at highspeed at a stage where no ringing is generated. Thus, an output circuitcan be obtained providing an output signal speedily and stably with noringing.

Embodiment 11

Referring to FIG. 75A, an output circuit 926 includes an invertercircuit 5 for inverting internal data signal ZDD, an AND circuit 3 forreceiving output signal of inverter circuit 5 and an output permissionsignal OEM, a drive transistor 1 rendered conductive in response to anoutput signal NOH of AND circuit 3 for charging output node 6 to thelevel of power supply voltage Vcc, and an AND circuit 4 for receivingoutput permission signal OEM and internal data signal ZDD, similar tothe conventional case.

Output circuit 926 further includes resistance elements 430, 432, and434 coupled in parallel to output node 6 and having different resistancevalues, a drive transistor 2 j responsive to an output signal NOL1 ofAND circuit 4 for coupling the other end of resistance element 430 tothe node of ground voltage GND, a rise delay circuit 440 for delayingthe rise of output signal NOL1 of AND circuit 4 for a predetermined timeperiod T9, a drive transistor 2 k rendered conductive in response to anoutput signal NOL2 of rise delay circuit 440 for coupling the other endof resistance element 432 to ground voltage GND, a rise delay circuit442 for delaying the rise of output signal NOL2 of rise delay circuit440 for a predetermined time of T10, and a drive transistor 21responsive to output signal NOL3 of rise delay circuit 442 for couplingthe other end of resistance element 434 to ground voltage GND level.Resistance elements 430, 432 and 434 have a large resistance value inthis order. The operation of the output circuit of FIG. 75A will bedescribed with reference to the operation waveform diagram of FIG. 75.

When output permission signal OEM and internal data signal ZDD bothattain an H level, output signal NOL1 of AND circuit 4 is pulled up toan H level. In response, drive transistor 2 j is turned on. Under thisstate, output node 6 is discharged to the level of ground voltage GNDvia resistance element 430 having a large resistance value. Resistanceelement 430 has the greatest current limiting function (the greatestresistance value). Therefore, the voltage dropping of output node 6 isrelatively mild. Then, at an elapse of time period T9, signal NOL2 fromrise delay circuit 440 is pulled up to an H level, whereby drivetransistor 2 k is turned on. Output node 6 is discharged to the level ofground voltage GND via of resistance element 432. Resistance element 432has a resistance value smaller than that of resistance element 430.Therefore, output node 6 is discharged in potential in a relatively mildmanner.

At an elapse of time T10 from the rise of signal NOL2, output signalNOL3 of rise delay circuit 422 is pulled up to an H level, whereby drivetransistor 21 is turned on. Resistance element 434 has the smallestresistance value. Therefore, output node 6 is discharged to the level ofground voltage GND at high speed. When drive transistor 21 is turned on,the voltage level of output node 6 is already lowered to the voltagelevel where ringing is not generated. Therefore, even when output node 6is discharged by drive transistor 21 at high speed, a stable outputsignal can be generated where no ringing is generated.

According to the structure shown in FIG. 75A, resistance elements 430,432 and 434 have different resistance values. Output node 6 isdischarged through resistance elements in the order of increasingresistance. This structure is advantageous over the structure in whichresistance elements of the same resistance value are provided inparallel to output node 6, as set forth in the following. Whenresistance elements having the same resistance value are provided inparallel, the combined resistance connected to output node 6 issequentially reduced. Therefore, output node 6 can be discharged at asequentially increasing speed. However, there is a possibility thatoutput node 6 is not discharged at high speed even when it arrives at avoltage level where ringing is not generated since the discharge rate isdetermined by the combined resistance value depending upon the number ofresistance elements. By employing a structure of different resistancevalues, the voltage of output node 6 can be discharged at high speedwhen it is lowered to a voltage level where ringing is not generated.Thus, an output signal can be generated at a higher speed.

The structure shown in FIG. 75A can be applied to a structure forcharging the output node 6.

Furthermore, according to the structure shown in FIG. 75A, a structuredifferentiating the ON-timing of drive transistors according toabsence/presence of an invalid output signal may be used together.Furthermore, a voltage adjuster providing voltages VccQ and VssQ to thepower supply node and the ground node may be used.

According to the eleventh embodiment in which a plurality of resistanceelements having different resistance values are connected in parallel toan output node so that the output node is charged/dischargedsequentially through resistance elements, starting from a resistanceelement having a greatest resistance value, the output node can becharged/discharged in a relatively mild manner when there is apossibility of generating of ringing, and then speedily driven to theminimum voltage level when arriving at a voltage level where ringing isnot generated. Thus, an output circuit can be obtained from which anoutput signal is generated at high speed with not ringing.

Embodiment 12

Referring to FIG. 76, an output circuit 926 includes a drive circuit 450for generating a data signal that is output according to an internaldata signal, an output permission signal, and if necessary, an outputdesignating signal DOT, and drive transistors 1 and 2 for providing anoutput signal Q to output node 6 according to an output signal of drivecircuit 450. The structure of output circuit 926 is similar to theprevious embodiments or the conventional structure.

Referring to FIG. 76, output circuit 926 further includes a referencevoltage generation circuit 470 supplied with a current from externalpower supply voltage extVcc supply node 455 for generating a referencevoltage VREF3 depending upon temperature and external power supplyvoltage extVcc, and a differential amplifier 460 for amplifyingdifferentially a constant reference voltage VREF1 independent oftemperature T and external power supply voltage extVcc and referencevoltage VREF3. One operating power supply voltage VccQ for outputcircuit 926 is applied from differential amplifier 460 to power supplynode 300. Differential amplifier 460 operates with external power supplyvoltage extVcc applied to supply node 455 as one operating power supplyvoltage. Reference voltage VREF1 is generated using a circuit similar tothat shown in FIG. 55B (provided that reference voltage VREF1 isgenerated from external power supply voltage extVcc).

Reference voltage generation circuit 470 includes a constant currentsource 471 for providing a constant current from supply node 455 to node475, and a MOS transistor 472 and a resistance element 473 connected inseries between node 475 and the ground voltage GND supply node. Externalpower supply voltage extVcc is applied to the gate of MOS transistor472. The structure of reference voltage generation circuit 470 issimilar to that shown in FIG. 56C provided that reference voltage VREF3is generated from external power supply voltage extVcc. Morespecifically, resistance element 473 is formed of polysilicon or using adiffused resistor having ions of high concentration implanted, and has apositive temperature coefficient. Resistance value R of resistanceelement 473 is set slightly greater than the ON resistance of MOStransistor 472. The temperature dependency of resistance value R ofresistor 473 is set sufficiently greater than the temperature dependentcharacteristic of constant current source 271 and the temperaturedependent characteristic of ON-resistance of MOS transistor 472.

MOS transistor 472 functions as a variable resistance element providinga conductance varied according to external power supply voltage extVcc.The operation of reference voltage generation circuit 470 is similar tothe reference voltage generation circuit shown in FIG. 56C.

Therefore, details will not be repeated. Reference voltage generationcircuit 470 generates reference voltage VREF3 having a negativedependency on external power supply voltage extVcc as shown in FIG. 77Aand a positive dependent characteristics with respect to ambienttemperature (operating temperature) as shown in FIG. 77B.

Differential amplifier 460 amplifies the difference of referencevoltages VREF3 and VREF1. When the operating temperature (ambienttemperature) T rises, reference voltage VREF3 is increased. In response,voltage VccQ provided from differential amplifier 460 is increased. Whenambient temperature (operating temperature) T is constant and externalpower supply voltage extVcc is increased, reference voltage VREF3 islowered, whereby voltage VccQ provided from differential amplifier 460is reduced. More specifically, differential amplifier 460 provides topower supply node 300 a voltage VccQ having a positive dependency withrespect to the operating temperature (ambient temperature) T as shown inFIG. 78A and a negative dependency with respect to external power supplyvoltage extVcc as shown in FIG. 78B. The effect of voltage VccQ havingsuch characteristics will be described.

As described with reference to FIGS. 56-59, an MOS transistor is reducedin operating rate due to generation of hot electrons in a channel regionupon a higher operating temperature, and increased in operating rate dueto increase in the drain current upon a higher gate potential or drainpotential (in the case of an n channel MOS transistor). When externalpower supply voltage extVcc increases, the operating speed of drivetransistor 1 is increased since a voltage changing in proportion toexternal power supply voltage extVcc is applied to power source node300. In a structure where the potential of output node 6 is prechargedto the level of an intermediate potential, the operating speed of drivetransistor 2 differs from that of drive transistor 1. Therefore, thetime required for providing a signal of an H level differs from the timerequired for providing a signal of an L level. This means that theoperating characteristic of the output circuit is degraded. In thiscase, increase in the operating speed of drive transistor 1 can besuppressed by reducing voltage VccQ applied to power supply node 300using differential amplifier 460. Therefore, change in the access timein providing a signal of an H level can be suppressed to maintain theoperating characteristic unchangedly. Similarly, when ambienttemperature (operating temperature) T is increased, the operating speedof drive transistors 1 and 2 are reduced. In this case, the reduction inoperating speed of drive transistor 1 can be compensated for byincreasing power supply voltage VccQ on power supply node 300.Therefore, the ascertaining timing of an output signal may be maintainedunchangedly.

By providing a structure in which a voltage at the level of VccQ andvarying similarly to power supply voltage VccQ is applied to the gatesof drive transistors 1 and 2 using a level conversion circuit as shownby the dotted line in the structure of FIG. 76, a stable output circuitcan be obtained that can have the output signal ascertaining timingconstant independent of external power supply voltage extVcc and ambienttemperature (operating temperature) T.

FIG. 79 schematically shows an entire structure of a semiconductordevice to which the present invention is applied. Referring to FIG. 79,a semiconductor device includes a voltagedown converter 480 forgenerating a constant internal voltage Vcc independent of external powersupply voltage extVcc being in a predetermined range, an internal powersupply usage circuit 482 operating with internal power supply voltageVcc applied from voltagedown converter 480 onto an internal power supplyline 303 and ground voltage GND applied onto ground line 302 as bothoperating power supply voltages, and an input/output circuit 484operating with external power supply voltage extVcc applied to powersupply node 300 and ground voltage GND applied to ground node 302 asboth operating power supply voltages to establish interface with theoutside world. According to the structure shown in FIG. 79, thecomponents in the system external to the device operates with externalpower supply voltage extVcc as the operating power supply voltage. Inthis case, input/output circuit 484 uses external power supply voltageextVcc as the operating power supply voltage in order to establishinterface with an external device. By applying a structure in FIG. 76 tothe output circuit in input/output circuit 484, a stable output signalindependent of external power supply voltage extVcc and ambienttemperature (operating temperature) can be generated. Furthermore, thesignal output timing can be made constant.

It is to be noted that in a structure shown in FIG. 76, power supplyvoltage VccQ applied to power supply node 300 may be provided to drivecircuit 450 as well as drive transistor 1. In output circuit 926, acircuit for converting the level of internal power supply voltage Vcc tothe level of external power supply voltage extVcc for provision to thegates of drive transistors 1 and 2 may be provided for drive circuit450.

According to the twelfth embodiment of the present invention in which avoltage maintaining positive dependency on ambient temperature andnegative dependency on an external power supply voltage is transmittedto the power supply node of the output circuit, an output circuit can beprovided that compensates for change in the operating characteristics ofa drive element due to variation in ambient temperature and externalpower supply voltage for generating an output signal of no ringingstably at constant timing.

In the output circuit of the present twelfth embodiment, a structurewhere the output node driving timing is differentiated shown in theprevious first to sixth embodiment may be used in combination.

Embodiment 13

Referring to FIG. 80A, in order to provide voltage VccQ onto powersupply node 300 in an output circuit 926, output circuit 926 includes adifferential amplifier 490 activated in response to a clock signal φCKfor amplifying differentially a voltage VccQ on power supply node 300and reference voltage VREFa, a p channel MOS transistor 492 coupledbetween a power supply node (the supply node of an internal power supplyvoltage or an external power supply voltage) and responsive to an outputsignal C1 of differential amplifier 490 for supplying a current fromthis power supply voltage supply node 491 to power supply node 300, anda switching transistor 494 formed of an n channel MOS transistor andresponsive to a clock signal /φCK for discharging power supply node 300to the level of ground voltage GND.

Clock signal φCK is rendered active at the activation of outputpermission signal OEM, for example, or clock signal φCK is renderedactive in response to a signal providing the operation timing of outputcircuit 926. The operation of the circuit shown in FIG. 80A will bedescribed with reference to the operation waveform diagram of FIG. 80B.

When clock signal φCK is inactive at the state of an L level,differential amplifier 490 is at an inactive state. Output signal C1 isat the level of voltage Vcc applied to power supply voltage supply node491. Drive transistor 492 is turned on. In contrast, clock signal /φCKis at an H level, and switching transistor 494 is turned on. The voltageVccQ on power supply node 300 is at the level of ground voltage GND.Drive transistors 1 and 2 in output circuit 926 are both turned off, andoutput node 6 is precharged to the level of an intermediate voltage, ormaintained at the potential level of the output signal read out at apreceding cycle (set to an output high impedance state).

When a data signal is newly read out, clock signal φCK attains an Hlevel of activation simultaneous to or earlier than output permissionsignal OEM, whereby differential amplifier 490 is activated. Incontrast, clock signal/φCK is driven to an L level, whereby switchingtransistor 494 is turned off. When voltage VccQ on power supply node 300is lower than the level of reference voltage VREFa, output signal C1from differential amplifier 490 is lowered from the H level (level ofvoltage Vcc), whereby drive transistor 492 is turned on. A current issupplied to power supply node 300 from power supply voltage supply node491, whereby voltage VccQ is raised. By setting appropriately thecurrent driving capability of drive transistor 492, voltage VccQ onpower supply node 300 is pulled up gently. When voltage VccQ on powersupply node 300 becomes higher than reference voltage VREFa, the outputsignal of differential amplifier 490 is pulled up to an H level, wherebydrive transistor 492 is turned off. As a result, voltage VccQ on powersupply node 300 is maintained at the voltage level of reference voltageVREFa.

When a signal of an H level is output in output circuit 926, drivetransistor 1 is turned on, and a current is supplied from power supplynode 300 to output node 6. The change in the voltage level of outputnode 6 is substantially equal to the change of voltage VccQ on powersupply node 300. The changing rate of voltage VccQ on power supply node300 is determined by the current driving capability of drive transistor492 and the parasitic capacitance accompanying power supply node 300.

The parasitic capacitance in power supply node 300 is inherent to thecircuit, and takes substantially a constant value. Therefore, byadjusting the current driving capability of drive transistor 492 to anappropriate value, the changing rate of voltage VccQ can be adjustedappropriately. Therefore, generation of ringing in output signal Q atoutput node 6 can be suppressed.

By adjusting the changing rate of output signal C1 of differentialamplifier 490, the current driving capability of drive transistor 492can be changed at an appropriate speed. Accordingly, the changing speedof output signal Q of output node 6 can be set such that no ringing isgenerated.

By setting reference voltage VREFa to a level where no ringing isgenerated when output node 6 is driven even at high speed, output node 6arrives at the level of reference voltage VREFa at a relatively highspeed. Meanwhile, by employing a structure where the voltage on powersupply node 300 is increased to the level of power supply voltage Vcc bya separate circuit, output signal Q can be provided speedily and stablywith no ringing.

Reference voltage VREFa takes a level higher than the high level voltageof VOH defined in the specification.

According to the present thirteenth embodiment in which power supplyvoltage VccQ to the power supply node of output circuit 926 is appliedby a differential amplifier activated in response to a signal providingthe operating timing of output circuit 926 and a drive transistorresponsive to an output signal of the differential amplifier forsupplying a current from the power voltage supply node to the powersupply node, the output signal appearing on the output node can bevaried according to the changing rate of voltage VccQ on power supplynode 300. Therefore, a stable output signal can be provided speedilywith no ringing.

Embodiment 14

FIG. 81 schematically shows the structure of the portion associated withoutput of a data signal in a semiconductor device according to afourteenth embodiment. Referring to FIG. 81, a semiconductor device 500includes memory cell arrays 501 and 502 each including a plurality ofmemory cells arranged in a matrix, and a data bus amplifier 504 foramplifying data of a selected memory cell in memory cell arrays 501 and502 for transmitting the amplified data onto an internal data bus 506. Astructure may be employed where memory cell arrays 501 and 502 areactivated simultaneously and data of selected memory cells in respectivememory cell arrays are read out at the same time. Furthermore, astructure may be employed where only one of memory cell arrays 501 and502 is activated and data is read out from a selected memory cell of theactivated memory cell array.

Since a data signal of a plurality of bits is output in semiconductormemory device 500, a plurality of pads 510 a-510 c and 510 d-510 f areprovided. Output circuits 926 a-926 c and output circuits 926 d-926 fare provided corresponding to each of pads 510 a-510 f between internaldata bus 506 and pads 510 a-510 f. As shown in FIG. 81, internal databus 506 from data bus amplifier 504 to output circuits 626 a-626 fdiffers in length. In FIG. 81, output circuits 926 a-926 c and outputcircuits 926-926 f are arranged in a symmetrical manner in semiconductordevice 500. In this case, the path of internal data bus 506 from databus amplifier 504 to output circuits 926 a, 926 d is the shortest, andthe path of internal data bus 506 from data bus amplifier 504 to outputcircuits 926 c and 926 f is the longest.

Output circuits 926 a-926 c are reduced in time constant for generatingoutput signal Q as a function of distance from data bus amplifier 504(as the length of internal data bus 506 is increased), whereby thechanging rate of output signal Q is increased. Similarly, outputcircuits 926 d-926 f has the time constant of output signal Q reduced asthe distance from data bus amplifier 504 is increased.

In the case where a plurality of drive transistors are provided inparallel for driving a plurality of output nodes with differentON-timings of the drive transistors, the difference in the ON-timings ofthe drive transistors in output circuits 926 a is set greater than thatof output circuit 926 c. Similarly, the time difference in ON-timing ofthe plurality of drive transistors in output circuit 926 d is setgreater than that of output circuit 926 f. The operation will now bedescribed.

First, the operation in a case where the time constant of an outputsignal is reduced in proportion to the distance from data bus amplifier504 will be described with reference to FIG. 82A. FIG. 82A representsthe operation in the case where output signals Qa and Qc are driven toan H level from an L level according to internal data signal IQaprovided to output circuit 926 a and an internal data signal IQcprovided to output circuit 926 c.

Data bus amplifier 504 is activated in response to a preamplifier enablesignal not shown, for amplifying the data of a plurality of memory cellsselected in memory cell array 501 and/or 502 to transmit the amplifiedmemory cell data of plurality of bits on internal data bus 506. As aresult, internal signals IQa and IQc on internal data bus 506 are variedaccording to the amplified signals. The parasitic capacitance andinterconnection resistance is increased in proportion to the lengthinternal data bus 506. Therefore, internal data signal IQa changesrelatively faster than internal data signal IQc. FIG. 82A shows thestate where internal data signal IQa arrives at an H level of apredetermined voltage level at time tb.

Output circuits 926 a-926 c and output circuits 926 d-926 f areactivated at the same timing according to output permission signal OEM(not shown). Output circuit 926 a has the current driving capability setlow, and the time constant of output signal Qa set to a great value. Thechanging of output signal Qa is relatively mild. In contrast, outputcircuit 926 has the time constant of output signal Qc set to a lowvalue. More specifically, the current driving capability of outputcircuit 926 c is set relatively high. Therefore, output signal Qc isdriven according to internal data signal IQ at a relatively high speed.Since internal data signal IQa changes at high speed and the currentdriving capability of output circuit 926 a is set low, output signal Qafrom output circuit 926 a changes in a relatively gentle manner. Incontrast, output circuit 926 c has the current driving capability sethigh although internal data signal IQc varies in a relatively mildmanner. Therefore, the gentle changing of internal data signal IQc iscompensated for, so that output signal Qc changes in a relatively mildmanner. As a result, the changing rate of output signals Qc and Qa ofoutput circuits 926 c and 926 a can be made equal, so that anascertained state of the output signals can be obtained at substantiallythe same timing.

FIG. 82A shows an example of a state where data output signals Qa and Qcare set at an ascertained state at time tc. The current drivingcapability of output circuit 926 a that receives internal data signalIQa changing speedily is set small. Therefore, generation of ringing issuppressed in output signal Qa even when internal data signal IQachanges at high speed. In output circuit 926 c receiving internal datasignal IQc changing in a relatively mild manner, the changing rate ofinternal data signal IQc is relatively show although the current drivingcapability is set high. By generating a signal Qc with a great drivingcurrent capability, the mild change of internal data signal IQc iscompensated for to allow generation of output signal Qc speedily. Evenwhen the current driving capability of output circuit 926 c is set high,output signal Qc can be generated at high speed with no ringing as longas the change in the output signal level of the internal AND circuitfollows the changing rate of internal data signal IQc. By this series ofoperations, output signals that attain an ascertained state stably atsubstantially the same timing can be generated to pads 110 a-110 c and110 d-110 f.

The operation in the case where the output circuit includes two drivetransistors which are turned on at different timings will be describedwith reference to FIG. 82B. FIG. 82B shows the input/output relationshipof data of output circuits 926 a and 926 c. FIG. 82B shows the casewhere internal data signals IQa and IQc both attain an H level, andoutput signals Qa and Qc from output circuits 926 a and 926 c are drivento an H level.

When data bus amplifier 504 is activated so that internal data signalsIQa and IQc on internal data bus 506 are changed, output circuits 926a-926 c and 926-926 f are activated at an elapse of a predetermined timeperiod. Internal data signal IQa for output circuit 926 a attains astable state at time tb. Responsively, output circuit 926 a providesoutput signal Qa with a relatively low driving capability. Therefore,data signal Qa varies in a relatively mild manner (charged by atransistor having a small current driving capability). Then at time tc,the drive transistor of a great current driving capability is turned onin output circuit 926, whereby output signal Qa is charged to the levelof a predetermined voltage at high speed. Here, output signal Qa isalready raised to a voltage level where no ringing is generated.Therefore, a stable output signal can be provided with no ringing evenwhen internal signal Qa is driven to a predetermined voltage level athigh speed. In contrast, internal data signal IQc changes in arelatively mild manner. In this case, output circuit 926 c chargesoutput signal Qc with the drive transistor of a small driving capabilityturned on. At time td, a drive transistor of a great current drivingcapability in output circuit 926 c is turned on, and output signal Qc ischarged at high speed. Here, internal data signal IQc varies in arelatively mild manner. Therefore, even when output signal Qc is changedby a great current driving capability by output circuit 926 c, thesignal voltage level applied to drive transistor 1 has not yet reached asufficient high voltage level (a predetermined final reaching voltagelevel) since internal data signal IQc changes mildly. The output node isdriven in a relatively mild manner, so that output signal Qc is drivento a high voltage level with no generation of ringing. When internaldata signal IQc reaches a predetermined voltage level, output signal Qcrises to a predetermined voltage level at high speed according tointernal data signal IQc.

By adjusting the current driving capability of an output circuitaccording to the distance from data bus amplifier 504 and adjusting thetime difference of the ON-timings of a plurality of drive transistors,the timing of the output signals from all the output circuits attainingan ascertained state can be set equal with no ringing, as shown in FIGS.82A and 82B. Thus, a semiconductor memory device of a short access timecan be realized.

FIGS. 82A and 82B show the state where the output circuit is activatedsimultaneously with the activation of data bus amplifier 504. However,the time difference of the activation timing of data bus amplifier 504and the activation timings of output circuits 926 a-926 f can be reducedeven in a structure where output circuits 926 a-926 f are activated(output permission signal OEM is rendered active) after the activationof data bus amplifier 504 followed by ascertation of the internal dataof data bus 506. Thus, a semiconductor memory device of a short accesstime can be realized.

[Modification 1]

In FIG. 83 showing a structure of a modification of the fourteenthembodiment of the present invention, the semiconductor device 500 isaccommodated in a package 550. Package 550 is provided with externallead terminals 515 a-515 c and 515 d-515 f. External lead terminals 515a-515 f are connected to pads 510 a-510 c and 510 d-510 f ofsemiconductor device 500 via the lead frame and bonding wires. In FIG.83, pads 510 a-510 f and external lead terminals 515 a-515 f areindicated as one straight line together with this bonding wires and leadframe. In a semiconductor device, the length of a lead frame differsaccording to the configuration of the package. As shown in FIG. 83, thecurrent driving capability of a drive transistor in the output circuitand the time difference in the ON-timings of a plurality of drivetransistors are adjusted according to a distance lf between pad 510 (510a-510 f) and external lead terminal 515 (515 a-515 f) and a distance ld(output circuit not shown in FIG. 83) between data bus amplifier 504 andpad 510.

For example, as the sum of the distance ld of internal data bus 506 andtotal distance lf of the bonding wire and the lead frame is smaller, thetime constant of output signal Q provided from the output circuit isincreased, so that the changing rate is slowed down (current drivingcapability of drive transistor is reduced). As the sum of distance ldand distance lf is smaller, the difference in time of the ON-timings ofa plurality of drive transistors is increased. If the distance lf of thelead frame and the bonding wire is great, the load to be driven by theoutput circuit is increased, and the changing rate of the output signalis reduced. Therefore, by increasing the driving capability of theoutput circuit in proportion to length lf, the large load can becompensated for and the output signal can be varied speedily. Accordingto such a structure, a semiconductor memory device can be obtained thatstabilizes the output signal from all output circuits at the same timingwith no ringing irrespective of the value of the sum of the distance ofthe internal data bus and the length of the bonding wire and the leadframe.

When the signal delay in an internal data bus is not so great as theinfluence of the length of the bonding wire and the lead frame withrespect to the input/output characteristics of an output circuit, thedriving capability of the output circuit may have the time constant ofoutput signal Q determined according to the value of the length lf ofthe bonding wire and the lead frame.

According to the fourteenth embodiment of the present invention in whichthe current driving capability of the drive transistor and the timedifference in the ON-timings of a plurality of drive transistors areadjusted according to the input and output load of the output circuit(the length of an internal data bus and an output signal line), ahigh-speed-operating semiconductor device is provided in which theoutput signals attain an ascertained state at the same timing in all theoutput circuits with no ringing.

Embodiment 15

FIG. 84 shows a structure of the portion related to discharging anoutput node to the level of ground voltage in an output circuitaccording to a fifteenth embodiment of the present invention. A similarstructure may be provided for the portion where output node 6 is chargedto the level of the voltage on power supply node 561. Referring to FIG.84, an output circuit includes a drive element 562 having a smallcurrent driving capability and responsive to an internal signal NOL1 fordischarging output node 6 to the level of ground voltage GND, and adrive element 564 having a large current driving capability andresponsive to a drive signal NOL2 rendered active at the timing laterthan that of internal signal NOL1 for discharging output node to thelevel of ground voltage. Output node 6 is connected to pad 560. Driveelement 564 of a great current driving capability is located near pad560. Drive transistors 2 a and 2 b are representatively shown in FIG. 84since drive elements 562 and 564 may include a resistance elementinternally.

Drive transistor 2 b of a great current driving capability has a channelwidth greater than that of drive transistor 2 a of a small currentdriving capability. More specifically, the junction area between theimpurity region to which output node 6 is connected and the substrateregion is greater in drive transistor 2 b than in drive transistor 2 a.Similarly, the area of the gate insulating film is greater in drivetransistor 2 b than in drive transistor 2 a. Therefore, drive transistor2 b has smaller drain electric field than drive transistor 2 a toimplement a greater junction breakdown voltage even when the samedrain-gate voltage and drain-source voltage are applied to drivetransistors 2 a and 2 b. This is because drive transistor 2 b of alarger gate insulation film in area has an dielectric breakdown voltagegreater than that of drive transistor 2 a, and the interelectrodeelectric field of the capacitor is inversely proportional to thecapacitor area. When a resistance element is used, the voltage drop ofthe resistance element of a greater resistance value is increased.

By using the structure shown in FIG. 84, a great noise such as a surgevoltage in output pad 560, when generated, can be absorbed by drivetransistor 2 b having a great junction breakdown voltage or a greatdielectric breakdown voltage. Therefore, drive transistor 2 a of a smalljunction breakdown voltage or a small dielectric breakdown voltage canbe prevented from receiving excessive noise. Thus, an output circuitsuperior in immunity to excessive noise can be obtained without anyparticular protection devices.

In the structure shown in FIG. 84, power supply voltage Vcc may beapplied to power supply node 561, and voltage VccQ provided from anotherpower supply circuit as described in the previous embodiment may beapplied.

The number of drive elements connected in parallel to this output nodemay be greater than 2. In this case, the drive element having thegreatest current driving capability is positioned closest to output pad560.

According to the fifteenth embodiment of the present invention in whicha drive element having the greatest current driving capability out of aplurality of drive elements with different current driving capabilitiesis located closest to the output pad, excessive noise such as of surgevoltage generated at the output pad can be absorbed by the drive elementof the greatest current driving capability. Thus, an output circuit ofhigh reliability superior in noise immunity can be obtained with noparticular protection devices.

Embodiment 16

FIG. 85 shows a structure of the portion that discharges output node 6to the level of ground voltage in an output circuit according to thesixteenth embodiment.

A similar structure can be provided to the portion where output node 6is charged to the level of the voltage on power supply node 561(transistor 1 is representatively shown). Transistor 1 is shown to beprotected by a protection circuit 570.

Referring to FIG. 85, an output circuit includes a plurality of driveelements of different current driving capabilities connected in parallelto output node 6. Drive element 562 of the smallest current drivingcapability is shown in FIG. 85. Similarly to the previous embodiments,drive element 562 has various applicable structures, and only drivetransistor 2 a is representatively shown. Output node 6 is connected tooutput pad 560. Protection circuit 570 is provided at the position ofthe output node between drive element 562 of a low current drivingcapability and power supply pad 560. As an example, protection circuit570 includes a diode 571 having a cathode connected to power supply node561 and an anode connected to output node 6, and a diode 574 having acathode connected to output node 6 and an anode connected to receiveground voltage GND. The drive element of a large current drivingcapability may be provided in either position F or G indicated by thearrows in FIG. 85.

Protection circuit 570 is to be provided between a drive element havingthe possibility of being damaged by excessive noise such as a surgevoltage of small current driving capability and output pad 560.

According to the structure shown in FIG. 85, diode 572 conducts when apositive excessive noise is generated at output pad 560. This positiveexcessive noise is discharged towards power supply node 561, and theexcess noise is absorbed. When a negative excessive noise is generated,diode 574 is rendered conductive, whereby the negative excessive voltageis charged towards the level of the ground voltage. As a result,excessive noise such as a positive or negative surge voltage is absorbedby protection circuit 570. Therefore, drive transistor 2 a of a smalljunction breakdown voltage and small dielectric breakdown voltage can beprevented from being damaged by excessive noise. The same applies evenif a resistance element is employed in the drive elements.

A structure in which voltage VccQ is applied to power supply node 561may be combined to the structure of FIG. 85. Although protection circuit570 is shown being formed of a diode, any structure can be used as longas it has a protection function of absorbing excessive noise such as asurge voltage.

Although output charging transistor 1 is provided at a preceding, orupstream stage of protection circuit 570, it may be provided betweenprotection circuit 570 and pad 560 when transistor 1 has a relativelylarge current driving capability.

In accordance with the sixteenth embodiment in which a protectioncircuit is provided between a drive element of a small current drivingcapability and an output pad to absorb excessive noise, such excessivenoise can be absorbed by the protection circuit even when it isgenerated at the output node via the output pad. The excessive noisewill not be transmitted to the drive element having a small currentdriving capability, so that the drive element of small current drivingcapability is prevented from being damaged. Thus, an output circuithaving superior immunity to excessive noise can be obtained.

The above-described first to sixteenth embodiments of the presentinvention may be appropriately combined in various modifications.

In the above-described embodiment, the case where inverted data of amemory cell is transmitted to the data output circuitry in the dataoutput structure is described. The present invention is not limited tosuch embodiments, and the structure of the present invention can beapplied in the case where a non-inverted data is transmitted or in thecase where a complementary pair of data of inverted data andnon-inverted data are transmitted to the data output circuitry by onepair of data lines.

Although a structure is mainly described in which output data of an Llevel is provided in the above embodiments, the present invention isalso applicable to a path where data of an H level is provided.

Although the above-described embodiments are described mainly on oneoutput circuit, the structure of the present invention can be appliedfor the output circuitry of each bit in a multi-bit parallel outputstructure. Furthermore, the data output node and the data input node maybe shared in common or provided separately.

Although the output circuit is shown being formed only of an n channelMOS transistor in the above embodiments, the present invention isapplicable to an output circuit formed of a CMOS circuit in which n andp channel MOS transistors are both used.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1-62. (canceled)
 63. A semiconductor device comprising: an outputcircuit for transmitting a signal of a logic corresponding to a logic ofan internal signal on an internal node to an output pad via an outputsignal line; and a lead frame coupled to said output pad, wherein saidoutput circuit comprises: a first drive element coupled between saidoutput signal line and a reference voltage supply node, and responsiveto said internal signal for being rendered conductive for driving saidoutput signal line to a voltage level on said reference voltage supplynode with a first current driving capability, and a second drive elementconnected between said output signal line and said reference voltagesupply node, and arranged at a position closer to said output pad thansaid first drive element is, and rendered conductive at a timing laterthan said first drive element in response to said internal signal fordriving said output node to a potential level on said reference voltagenode with a second current driving capability greater than said firstcurrent driving capability.
 64. The semiconductor device according toclaim 63, wherein said output circuit further comprises a protectionelement coupled to said output line at a position between said outputpad and said first drive element, for emitting a surge voltage on saidoutput pad to said reference voltage supply node or to a second powersupply node.
 65. The semiconductor device according to claim 63, whereinsaid output pad is connected to said lead frame via a bonding wire. 66.The semiconductor device according to claim 63, wherein said firstdriving element comprises an insulated gate field transistor, and saidsecond drive element comprises an insulated gate field effect transistorhaving a junction capacitance between an impurity region and a substrateregion greater than said first drive element has.
 67. The semiconductordevice according to claim 64, wherein; said protection element iscoupled to said output line at a position between said first driveelement and said second drive element.